Patents by Inventor Chia-Lin Yu

Chia-Lin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210264566
    Abstract: A system for image scaling and enhancement is provided. The system includes a scaling processing unit, a deep-learning residue network unit and a combination unit. The filter scaling processing unit is configured to upscale a low-resolution image to output a high-resolution image. The deep-learning residue network unit is operated based on a deep-learning result, and configured to output a high-resolution residue image corresponding to the low-resolution image. The combination unit is configured to adjust the high-resolution residue image according to a weighting factor and combine an adjusted high-resolution residue image and the high-resolution image, in order to output an enhanced image, wherein the weighting factor is different from a reference weighting factor being used in a deep-learning procedure for training the deep-learning residue network unit.
    Type: Application
    Filed: July 9, 2020
    Publication date: August 26, 2021
    Inventors: Chia-Wei Yu, Yi-Ting Bao, Yen-Lin Chen, Shang-Yen Lin
  • Publication number: 20210005515
    Abstract: A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T1 at a first end of the opening, and a thickness T2 at a second end of the opening, and R1 is a ratio of T1 to T2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T3 at the first end of the opening, a thickness T4 at the second end of the opening, R2 is a ratio of T3 to T4, and R1 is greater than R2.
    Type: Application
    Filed: September 15, 2020
    Publication date: January 7, 2021
    Inventors: Chen-Hua YU, Cheng-Hung CHANG, Ebin LIAO, Chia-Lin YU, Hsiang-Yi WANG, Chun Hua CHANG, Li-Hsien HUANG, Darryl KUO, Tsang-Jiuh WU, Wen-Chih CHIOU
  • Patent number: 10784162
    Abstract: A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 10497619
    Abstract: A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the openings. A thickness of the substrate may be reduced from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening and the conductive material in the second opening. A light emitting diode (LED) device is connected to the third surface of the substrate.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chia-Lin Yu, Hung-Pin Chang, Chien Ling Hwang, Jui-Pin Hung, Yung-Chi Lin
  • Publication number: 20190067107
    Abstract: A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.
    Type: Application
    Filed: October 23, 2018
    Publication date: February 28, 2019
    Inventors: Chen-Hua YU, Cheng-Hung CHANG, Ebin LIAO, Chia-Lin YU, Hsiang-Yi WANG, Chun Hua CHANG, Li-Hsien HUANG, Darryl KUO, Tsang-Jiuh WU, Wen-Chih CHIOU
  • Publication number: 20180350678
    Abstract: A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the openings. A thickness of the substrate may be reduced from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening and the conductive material in the second opening. A light emitting diode (LED) device is connected to the third surface of the substrate.
    Type: Application
    Filed: August 10, 2018
    Publication date: December 6, 2018
    Inventors: Chen-Hua YU, Chia-Lin YU, Hung-Pin CHANG, Chien Ling HWANG, Jui-Pin HUNG, Yung-Chi LIN
  • Patent number: 10115634
    Abstract: A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 10062821
    Abstract: A light-emitting device comprises a plurality of light-emitting pillars separated from each other by a space, wherein each of the plurality of light-emitting pillars comprises a first conductivity type layer, an active layer on the first conductivity type layer, and a second conductivity type layer on the active layer; a reflective layer surrounding a sidewall of each of the plurality of light-emitting pillars; a top electrode formed on the reflective layer and the plurality of light-emitting pillars; and a fill material formed between the reflective layer and the top electrode.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 28, 2018
    Assignee: Epistar Corporation
    Inventors: Ding-Yuan Chen, Chia-Lin Yu, Chen-Hua Yu, Wen-Chih Chiou
  • Patent number: 10049931
    Abstract: A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the openings. A thickness of the substrate may be reduced from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening and the conductive material in the second opening. A light emitting diode (LED) device is connected to the third surface of the substrate.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semicondutor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Pin Chang, Yung-Chi Lin, Chia-Lin Yu, Jui-Pin Hung, Chien Ling Hwang
  • Patent number: 9827653
    Abstract: The screwing accessory device comprises a receiving box, a rack and a pushing component. The receiving box is for receiving the screwed component. The rack is connected to the receiving box. The pushing component is disposed within the receiving box and is used for pushing the screwed component.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: November 28, 2017
    Assignee: WISTRON CORPORATION
    Inventors: Jui-Kai Cheng, Chia-Lin Yu
  • Publication number: 20170271568
    Abstract: A light-emitting device comprises a plurality of light-emitting pillars separated from each other by a space, wherein each of the plurality of light-emitting pillars comprises a first conductivity type layer, an active layer on the first conductivity type layer, and a second conductivity type layer on the active layer; a reflective layer surrounding a sidewall of each of the plurality of light-emitting pillars; a top electrode formed on the reflective layer and the plurality of light-emitting pillars; and a fill material formed between the reflective layer and the top electrode.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Ding-Yuan CHEN, Chia-Lin YU, Chen-Hua YU, Wen-Chih CHIOU
  • Patent number: 9698325
    Abstract: A light-emitting device comprises a substrate; a plurality of light-emitting diodes formed on the substrate, wherein each of the plurality of light-emitting diodes comprises a first conductivity type layer, an active layer on the first conductivity type layer, and a second conductivity type layer on the active layer; a reflective layer surrounding a sidewall of each of the plurality of light-emitting diodes; and a top electrode formed on the reflective layer and the plurality of light-emitting diodes.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 4, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Ding-Yuan Chen, Chia-Lin Yu, Chen-Hua Yu, Wen-Chih Chiou
  • Publication number: 20160329245
    Abstract: A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.
    Type: Application
    Filed: July 20, 2016
    Publication date: November 10, 2016
    Inventors: Chen-Hua YU, Cheng-Hung CHANG, Ebin LIAO, Chia-Lin YU, Hsiang-Yi WANG, Chun Hua CHANG, Li-Hsien HUANG, Darryl KUO, Tsang-Jiuh WU, Wen-Chih CHIOU
  • Patent number: 9448585
    Abstract: A clamping structure includes an object, a clamping component and an elastic component. The object has a hole and a containing space, wherein the containing space is connected to the hole. The clamping component includes a pillar, a bump and a head portion, wherein the bump and the head portion are connected to the pillar, and the pillar is adapted to be inserted into the hole and rotated such that the bump moves to the containing space. When the bump is located in the containing space, the elastic component is compressed between the object and the head portion, and the bump is positioned at the containing space by elastic force of the elastic component, such that the clamping component is fastened to the object.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: September 20, 2016
    Assignee: Wistron Corporation
    Inventors: Jui-Kai Cheng, Chia-Lin Yu, Ju-Ching Lin, Ya-Jiun Tzeng, Chu-Ting Yang
  • Patent number: 9418923
    Abstract: A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20160197014
    Abstract: A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the openings. A thickness of the substrate may be reduced from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening and the conductive material in the second opening. A light emitting diode (LED) device is connected to the third surface of the substrate.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Inventors: Chen-Hua YU, Hung-Pin CHANG, Yung-Chi LIN, Chia-Lin YU, Jui-Pin HUNG, Chien Ling HWANG
  • Patent number: 9373755
    Abstract: A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: June 21, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Chen-Hua Yu, Hung-Ta Lin, Wen-Chih Chiou, Ding-Yuan Chen, Chia-Lin Yu
  • Patent number: 9305864
    Abstract: Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jaw-Juinn Horng, Chia-Lin Yu, Chung-Hui Chen, Der-Chyang Yeh, Yung-Chow Peng
  • Patent number: 9287440
    Abstract: A method of making a semiconductor device, the method includes forming a first opening and a second opening in a substrate. The method further includes forming a conductive material in the first opening and in the second opening, the conductive material comprising a joined portion where the conductive material in the first opening and the conductive material in the second opening are electrically and thermally connected together at a first surface of the substrate. The method further includes reducing a thickness of the substrate from a second surface of the substrate, opposite the first surface, to expose the conductive material in the first opening and the conductive material in the second opening. The method further includes connecting a device to the second surface of the substrate.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Pin Chang, Yung-Chi Lin, Chia-Lin Yu, Jui-Pin Hung, Chien Ling Hwang
  • Publication number: 20160064632
    Abstract: A light-emitting device comprises a substrate; a plurality of light-emitting diodes formed on the substrate, wherein each of the plurality of light-emitting diodes comprises a first conductivity type layer, an active layer on the first conductivity type layer, and a second conductivity type layer on the active layer; a reflective layer surrounding a sidewall of each of the plurality of light-emitting diodes; and a top electrode formed on the reflective layer and the plurality of light-emitting diodes.
    Type: Application
    Filed: October 29, 2015
    Publication date: March 3, 2016
    Inventors: Ding-Yuan CHEN, Chia-Lin YU, Chen-Hua YU, Wen-Chih CHIOU