Patents by Inventor Chia-Lin Yu
Chia-Lin Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140015146Abstract: A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.Type: ApplicationFiled: September 23, 2013Publication date: January 16, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua YU, Cheng-Hung CHANG, Ebin LIAO, Chia-Lin YU, Hsiang-Yi WANG, Chun Hua CHANG, Li-Hsien HUANG, Darryl KUO, Tsang-Jiuh WU, Wen-Chih CHIOU
-
Patent number: 8629465Abstract: A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency.Type: GrantFiled: January 25, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hung-Ta Lin, Wen-Chih Chiou, Ding-Yuan Chen, Chia-Lin Yu
-
Publication number: 20140008817Abstract: Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.Type: ApplicationFiled: September 12, 2013Publication date: January 9, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jaw-Juinn HORNG, Chia-Lin Yu, Chung-Hui Chen, Der-Chyang Yeh, Yung-Chow Peng
-
Publication number: 20130302979Abstract: A method of making a semiconductor device, the method includes forming a first opening and a second opening in a substrate. The method further includes forming a conductive material in the first opening and in the second opening, the conductive material comprising a joined portion where the conductive material in the first opening and the conductive material in the second opening are electrically and thermally connected together at a first surface of the substrate. The method further includes reducing a thickness of the substrate from a second surface of the substrate, opposite the first surface, to expose the conductive material in the first opening and the conductive material in the second opening. The method further includes connecting a device to the second surface of the substrate.Type: ApplicationFiled: July 15, 2013Publication date: November 14, 2013Inventors: Chen-Hua YU, Hung-Pin CHANG, Yung-Chi LIN, Chia-Lin YU, Jui-Pin HUNG, Chien Ling HWANG
-
Patent number: 8575725Abstract: A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.Type: GrantFiled: March 13, 2013Date of Patent: November 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
-
Patent number: 8546953Abstract: Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.Type: GrantFiled: December 13, 2011Date of Patent: October 1, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jaw-Juinn Horng, Chia-Lin Yu, Chung-Hui Chen, Der-Chyang Yeh, Yung-Chow Peng
-
Patent number: 8519414Abstract: A semiconductor structure includes a substrate and a conductive carrier-tunneling layer over and contacting the substrate. The conductive carrier-tunneling layer includes first group-III nitride (III-nitride) layers having a first bandgap, wherein the first III-nitride layers have a thickness less than about 5 nm; and second III-nitride layers having a second bandgap lower than the first bandgap, wherein the first III-nitride layers and the second III-nitride layers are stacked in an alternating pattern. The semiconductor structure is free from a III-nitride layer between the substrate and the conductive carrier-tunneling layer. The semiconductor structure further includes an active layer over the conductive carrier-tunneling layer.Type: GrantFiled: September 20, 2011Date of Patent: August 27, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Lin Yu, Ding-Yuan Chen, Chen-Hua Yu, Wen-Chih Chiou
-
Patent number: 8507940Abstract: The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip.Type: GrantFiled: September 10, 2010Date of Patent: August 13, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hung-Pin Chang, Yung-Chi Lin, Chia-Lin Yu, Jui-Pin Hung, Chien Ling Hwang
-
Patent number: 8487410Abstract: A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.Type: GrantFiled: April 13, 2011Date of Patent: July 16, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
-
Patent number: 8486807Abstract: A method of forming a semiconductor structure includes providing a substrate; forming a buffer/nucleation layer over the substrate; forming a group-III nitride (III-nitride) layer over the buffer/nucleation layer; and subjecting the III-nitride layer to a nitridation. The step of forming the III-nitride layer comprises metal organic chemical vapor deposition.Type: GrantFiled: December 17, 2010Date of Patent: July 16, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chia-Lin Yu, Ding-Yuan Chen, Wen-Chih Chiou
-
Publication number: 20130147057Abstract: Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.Type: ApplicationFiled: December 13, 2011Publication date: June 13, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jaw-Juinn HORNG, Chia-Lin YU, Chung-Hui CHEN, Der-Chyang YEH, Yung-Chow PENG
-
Patent number: 8377796Abstract: A method of forming a circuit structure includes providing a substrate; forming recesses in the substrate; forming a mask layer over the substrate, wherein the mask layer covers non-recessed portions of the substrate, with the recesses exposed through openings in the mask layer; forming a buffer/nucleation layer on exposed portions of the substrate in the recesses; and growing a group-III group-V (III-V) compound semiconductor material from the recesses until portions of the III-V compound semiconductor material grown from the recesses join each other to form a continuous III-V compound semiconductor layer.Type: GrantFiled: August 11, 2009Date of Patent: February 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Lin Yu, Chen-Hua Yu, Ding-Yuan Chen, Wen-Chih Chiou
-
Publication number: 20120261827Abstract: A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.Type: ApplicationFiled: April 13, 2011Publication date: October 18, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua YU, Cheng-Hung CHANG, Ebin LIAO, Chia-Lin YU, Hsiang-Yi WANG, Chun Hua CHANG, Li-Hsien HUANG, Darryl KUO, Tsang-Jiuh WU, Wen-Chih CHIOU
-
Patent number: 8252682Abstract: A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer.Type: GrantFiled: February 12, 2010Date of Patent: August 28, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ku-Feng Yang, Weng-Jin Wu, Hsin-Hsien Lu, Chia-Lin Yu, Chu-Sung Shih, Fu-Chi Hsu, Shau-Lin Shue
-
Publication number: 20120119236Abstract: A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency.Type: ApplicationFiled: January 25, 2012Publication date: May 17, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hung-Ta Lin, Wen-Chih Chiou, Ding-Yuan Chen, Chia-Lin Yu
-
Patent number: 8154038Abstract: A device structure includes a substrate; a group-III nitride layer over the substrate; a metal nitride layer over the group-III nitride layer; and a light-emitting layer over the metal nitride layer. The metal nitride layer acts as a reflector reflecting the light emitted by the light-emitting layer.Type: GrantFiled: July 1, 2008Date of Patent: April 10, 2012Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chen-Hua Yu, Wen-Chih Chiou, Ding-Yuan Chen, Chia-Lin Yu
-
Patent number: 8148732Abstract: A light-emitting diode (LED) device is provided. The LED device is formed on a substrate having a carbon-containing layer. Carbon atoms are introduced into the substrate to prevent or reduce atoms from an overlying metal/metal alloy transition layer from inter-mixing with atoms of the substrate. In this manner, a crystalline structure is maintained upon which the LED structure may be formed.Type: GrantFiled: July 24, 2009Date of Patent: April 3, 2012Assignee: Taiwan Semiconductor Manufacturing, Co., Ltd.Inventors: Chen-Hua Yu, Chia-Lin Yu, Ding-Yuan Chen, Wen-Chih Chiou, Hung-Ta Lin
-
Publication number: 20120068218Abstract: The present disclosure provides a method of packaging for a photonic device, such as a light-emitting diode device. The packaging includes an insulating structure. The packaging includes first and second conductive structures that each extend through the insulating structure. A substantial area of a bottom surface of the light-emitting diode device is in direct contact with a top surface of the first conductive structure. A top surface of the light-emitting diode device is bonded to the second conductive structure through a bonding wire.Type: ApplicationFiled: September 17, 2010Publication date: March 22, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Pin Chang, Yung-Chi Lin, Chia-Lin Yu, Jui-Ping Hung, Chien Ling Hwang, Chen-Hua Yu
-
Patent number: 8138076Abstract: MOSFETs having stacked metal gate electrodes and methods of making the same are provided. The MOSFET gate electrode includes a gate metal layer formed atop a high-k gate dielectric layer. The metal gate electrode is formed through a low oxygen content deposition process without charged-ion bombardment to the wafer substrate. Metal gate layer thus formed has low oxygen content and may prevent interfacial oxide layer regrowth. The process of forming the gate metal layer generally avoids plasma damage to the wafer substrate.Type: GrantFiled: May 12, 2008Date of Patent: March 20, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Tung Lin, Yung-Sheng Chiu, Hsiang-Yi Wang, Chia-Lin Yu, Chen-Hua Yu
-
Patent number: 8134163Abstract: A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency.Type: GrantFiled: October 8, 2008Date of Patent: March 13, 2012Assignee: Taiwan Semiconductor Manfacturing Co., Ltd.Inventors: Chen-Hua Yu, Hung-Ta Lin, Wen-Chih Chiou, Ding-Yuan Chen, Chia-Lin Yu