Abstract: A method includes depositing a first passivation layer over a conductive feature, wherein the first passivation layer has a first dielectric constant, forming a capacitor over the first passivation layer, and depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant. The method further includes forming a redistribution line over and electrically connecting to the capacitor, depositing a third passivation layer over the redistribution line, and forming an Under-Bump-Metallurgy (UBM) penetrating through the third passivation layer to electrically connect to the redistribution line.

Abstract: A method for beam management performed by a UE is provided. The method includes: receiving a DCI format in a first BWP based on a first QCL assumption specific to the first BWP, the DCI format scheduling a PDSCH reception in a second BWP; receiving an RRC configuration that includes a plurality of candidate TCI states associated with a serving cell in which the PDSCH is scheduled; receiving a MAC CE that indicates a subset of the plurality of candidate TCI states for activation in the second BWP; determining a second QCL assumption specific to the second BWP based on one TCI state in the subset; and receiving the PDSCH in the second BWP based on the second QCL assumption.

Abstract: A chip package is provided. The chip package includes a device substrate, a first redistribution layer (RDL), a carrier base, and at least one conductive connection structure. The device substrate has at least one first through-via opening extending from the backside surface of the device substrate to the active surface of the device substrate. The first RDL is disposed on the backside surface of the device substrate and extends in the first through-via opening. The carrier base carries the device substrate, and has a first surface facing the backside surface of the device substrate and a second surface opposite the first surface. The conductive connection structure is disposed on the second surface of the carrier base and is electrically connected to the first RDL.

Abstract: Uplink transmission performed by a UE is provided. The UE receives configured grant (CG) configurations for allocating a group of Physical Uplink Shared Channel (PUSCH) durations in a bandwidth part (BWP), each configured grant configuration having a priority level corresponding to the allocated PUSCH duration, wherein at least two of the PUSCH durations in the group overlap in a time domain; identifies a set of PUSCH durations for transmitting a medium access control (MAC) protocol data unit (PDU) generated from available data from the group of PUSCH durations; selects a PUSCH duration from the identified set of PUSCH durations as a prioritized PUSCH duration based on a comparison of the priority levels corresponding to the identified set of PUSCH durations; and transmits the MAC PDU, via the transceiver, on the prioritized PUSCH duration.

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Abstract: A method for performing camera modality adaptation in a simultaneous localization and mapping (SLAM) device is provided. The SLAM device includes a camera sensor and a SLAM processor. The method includes acquiring data from the SLAM device, and determining, based on the acquired data, an operational condition of the SLAM device. The method also includes deciding, based on the determined operational condition, a camera modality for the SLAM device. The method further includes controlling, based on the decided camera modality, a camera modality of an image sequence inputted into the SLAM processor.

Abstract: A method for performing frame rate adaptation in a simultaneous localization and mapping (SLAM) device is provided. The SLAM device includes a SLAM processor. The method includes: acquiring data from the SLAM device; determining, based on the acquired data, an operative condition of the SLAM device; deciding, based on the determined operative condition, a target frame rate for the SLAM device; and controlling, based on the decided target frame rate, a frame rate of an image sequence inputted into the SLAM processor.

Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.

Abstract: A chip package includes an application chip, a micro-electromechanical systems (MEMS) chip, a conductive element, a bonding wire, and a molding compound. The application chip has a conductive pad. The MEMS chip is located on the application chip, and includes a main body and a cap. The main body is located between the cap and the application chip. The main body has a conductive pad. The conductive element is located on the conductive pad of the main body of the MEMS chip. The bonding wire extends from the conductive element to the conductive pad of the application chip. The molding compound is located on the application chip and surrounds the MEMS chip. The conductive element and the bonding wire are located in the molding compound.

Abstract: A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.

Abstract: A chip package includes a carrier board, a chip, a light transmissive sheet, a supporting element, and a molding material. The chip is located on the carrier board and has a sensing area. The light transmissive sheet is located above the supporting element and covers the sensing area of the chip. The supporting element is located between the light transmissive sheet and the chip, and surrounds the sensing area of the chip. The molding material is located on the carrier board and surrounds the chip and the light transmissive sheet. A top surface of the molding material is lower than a top surface of the light transmissive sheet.

Abstract: A chip package includes a chip, a first support layer, a light emitter, a first light transmissive sheet, a redistribution layer, and a conductive structure. A top surface of the chip has a conductive pad and a first light receiver. The first support layer is located on the top surface of the chip. The light emitter is located on the top surface of the chip. The first light transmissive sheet is located on the first support layer and covers the first light receiver. The redistribution layer is electrically connected to the conductive pad and extends to a bottom surface of the chip. The conductive structure is located on the redistribution layer that is on the bottom surface of the chip.

Abstract: A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.

Abstract: A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

Abstract: A chip package is provided. The chip package includes a first semiconductor chip, a second semiconductor chip, a first encapsulating layer, a second encapsulating layer, a first through-via, and a second through-via. The second semiconductor chip is stacked on the first semiconductor chip, and the first encapsulating layer and the second encapsulating layer surround the first semiconductor chip and the second semiconductor chip, respectively. In addition, the first through-via and the second through-via penetrate the first encapsulating layer and the second encapsulating layer, respectively, and the second through-via is electrically connected between the second semiconductor chip and the first through-via. A method for forming the chip package are also provided.

Abstract: A chip package includes a sensing element, a dam layer, and a light transmissive cover. A surface of the sensing element has a sensing area and a conductive pad. The conductive pad is adjacent to an edge of the surface of the sensing element. The dam layer is located on the surface of the sensing element and surrounds the sensing area. The dam layer has a main portion and plural mark portions. The mark portions are respectively located in plural corners of the main portion, located in a sidewall of the main portion, respectively located on plural corners of the sensing element, respectively located on plural inner edges of the main portion, or respectively located on plural outer edges of the main portion. The light transmissive cover is located on the dam layer.

Abstract: A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

Abstract: A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.

Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.