Abstract: An auto-convergence system includes a disparity unit, a convergence unit and an active learning unit. The disparity unit performs a disparity analysis upon an input stereo image pair, and accordingly obtains a disparity distribution of the input stereo image pair. The convergence unit adjusts the input stereo image pair adaptively according to the disparity distribution and a learned convergence range, and accordingly generates an output stereo image pair for playback. The active learning unit actively learns a convergence range during playback of stereo image pairs, and accordingly determines the learned convergence range.

Abstract: A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract: A fabrication method of a semiconductor stack structure mainly includes: singulating a wafer of a first specification into a plurality of chips; rearranging the chips into a second specification of a wafer so as to stack the chips on a substrate of the second specification through a plurality of blocks; forming a redistribution layer on the chips; and performing a cutting process to obtain a plurality of semiconductor stack structures. Therefore, the present invention allows a wafer of a new specification to be processed by using conventional equipment without the need of new factory buildings or equipment. As such, chip packages can be timely supplied to meet the replacement speed of electronic products.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.

Abstract: The present invention provides a chip package that includes a semiconductor chip, at least one recess, a plurality of first redistribution metal lines, and at least one protrusion. The semiconductor chip has a plurality of conductive pads disposed on an upper surface of the semiconductor chip. The recess extends from the upper surface to a lower surface of the semiconductor chip, and is arranged on the side of the semiconductor chip. The first redistribution metal lines are disposed on the upper surface, electrically connected to the conductive pad individually, and extended into the recesses separately. The protrusion is disposed in the recess and located between the adjacent first redistribution metal lines.

Abstract: A chip package includes a semiconductor chip, insulation layer, redistribution layer and packaging layer and is formed with a cavity. The semiconductor chip has an electronic component and a conductive pad. The conductive pad and the electronic component are disposed on an upper surface of the semiconductor chip and electrically connected. The cavity opens from a lower surface of the semiconductor chip and tapers toward the upper surface to expose the conductive pad. The insulation layer coats the lower surface and a portion of the cavity. The insulation layer is formed with a gap to expose the conductive pad. The redistribution layer coats the lower surface and a portion of the cavity and is electrically connected to the conductive pad through the gap. The packaging layer coats the lower surface and a portion of the cavity.

Abstract: An image processing method includes: receiving a plurality of images, the images being captured under different view points; and performing image alignment for the plurality of images by warping the plurality of images, where the plurality of images are warped according to a set of parameters, and the set of parameters are obtained by finding a solution constrained to predetermined ranges of physical camera parameters. In particular, the step of performing the image alignment further includes: automatically performing the image alignment to reproduce a three-dimensional (3D) visual effect, where the plurality of images is captured by utilizing a camera module, and the camera module is not calibrated with regard to the view points. For example, the 3D visual effect can be a multi-angle view (MAV) visual effect. In another example, the 3D visual effect can be a 3D panorama visual effect. An associated apparatus is also provided.

Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess.

Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess. A method for forming the chip package is also provided.

Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.

Abstract: An embodiment of the invention provides a chip package, which includes: a substrate having an upper surface and a lower surface; a passivation layer located overlying the upper surface of the substrate; a plurality of conducting pad structures disposed overlying the upper surface of the substrate, wherein at least portions of upper surfaces of the conducting pad structures are exposed; a plurality of openings extending from the upper surface towards the lower surface of the substrate; and a plurality of movable bulks located between the openings and connected with the substrate, respectively, wherein each of the movable bulks is electrically connected to one of the conducting pad structures.

Abstract: A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from the second surface towards the first surface and correspondingly exposing the conducting pads, wherein a first opening of the openings and a second opening of the openings next to the first opening respectively expose the first and the second conducting pads and extend along a direction intersecting the side surface of the substrate to respectively extend beyond the first and the second conducting pads; and a first and a second wire layers located on the second surface and extending into the first the second openings to electrically contact with the first and the second conducting pads, respectively.

Abstract: A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second substrate has a plurality of rectangular chip regions separated by a scribed-line region. A portion of the second substrate corresponding to the scribed-line region is removed to form a plurality of chips on the first substrate, wherein at least one bridge portion is formed between adjacent chips. A chip package formed by the method is also provided.

Abstract: An on-line stereo camera calibration method employed by an electronic device with a stereo camera device includes: retrieving a feature point set, and utilizing a stereo camera calibration circuit on the electronic device to calculate a stereo camera parameter set based on the retrieved feature point set. In addition, an on-line stereo camera calibration device on an electronic device with a stereo camera device includes a stereo camera calibration circuit. The stereo camera calibration circuit includes an input interface and a stereo camera calibration unit. The input interface is used to retrieve a feature point set. The stereo camera calibration unit is used to calculate a stereo camera parameter set based on at least the retrieved feature point set.

Abstract: A stereo preview apparatus has an auto-stereoscopic display, an input interface, a motion detection circuit, and a visual transition circuit. The input interface receives at least an input stereo image pair including a left-view image and a right-view image generated from an image capture device. The motion detection circuit evaluates a motion status of the image capture device. The visual transition circuit generates an output stereo image pair based on the input stereo image pair, and outputs the output stereo image pair to the auto-stereoscopic display for stereo preview, wherein the visual transition circuit refers to the evaluated motion status to configure adjustment made to the input stereo image pair when generating the output stereo image pair.

Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

Abstract: A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from the second surface towards the first surface and correspondingly exposing the conducting pads, wherein a first opening of the openings and a second opening of the openings next to the first opening respectively expose the first and the second conducting pads and extend along a direction intersecting the side surface of the substrate to respectively extend beyond the first and the second conducting pads; and a first and a second wire layers located on the second surface and extending into the first the second openings to electrically contact with the first and the second conducting pads, respectively.

Abstract: A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.

Abstract: A photographic system for generating photos is provided. The photographic system comprises a photo composition unit, and a photo synthesizer. The photo composition unit is capable of determining an extracted view from a three dimensional (3D) scene. The photo synthesizer, coupled to the photo composition unit, is capable of synthesizing an output photo according to the extracted view.