Abstract: An embodiment of this invention provides a separation apparatus for separating a stacked article, such as a semiconductor chip package with sensing functions, comprising a substrate and a cap layer formed on the substrate. The separation apparatus comprises a vacuum nozzle head including a suction pad having a top surface and a bottom surface, a through hole penetrating the top surface and the bottom surface of the suction pad, and a hollow vacuum pipe connecting the through hole to a vacuum pump; a stage positing under the vacuum nozzle head and substantially aligning with the suction pad; a control means coupling to the vacuum nozzle head to lift upward or lower down the vacuum nozzle head; and a first cutter comprising a first cutting body and a first knife connecting to the first cutting body.

Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess.

Abstract: A support base for an electronic device includes a base, a trigger mechanism and an operating mechanism. The base includes a limit rib. The trigger mechanism includes a trigger member and a swing member. The trigger member is movably disposed on the base and therefore has an untriggered position and a triggered position. The swing member is pivoted on the trigger member and therefore has a pressed position and a room-making position. The operating mechanism is movably disposed on the base and therefore has a first operating position and a second operating position. The operating mechanism has an operating end and a moving end opposite to each other. The moving end corresponds to the swing member and is used for rotating relative to the operating end. When the operating mechanism is at the first operating position, the moving end of the operating mechanism is hooked at the limit rib.

Abstract: A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.

Abstract: A support bracket includes a housing, a driving member, a first linking member, a gear mechanism, a first engaging member, a second linking member and a second engaging member. The housing has a guiding rail and a through hole. The driving member has a driving portion and a first rack portion, and the driving portion is exposed out of the housing. The first linking member has a second rack portion and an engaging groove. The gear mechanism meshes with the first rack portion and the second rack portion. The first engaging member has a guiding portion and a first engaging portion, and the guiding portion is disposed in the guiding rail. Opposite ends of the second linking member are pivotally connected to the first linking member and the first engaging member, respectively. The second engaging member has a second engaging portion.

Abstract: A chip device package and a fabrication method thereof are provided. The chip device package includes a semiconductor substrate having a first surface and an opposing second surface. A recessed portion is disposed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the second surface of the semiconductor substrate. A protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion. A through hole is disposed on the first surface of the semiconductor substrate. A buffer material that is different from the material of the protection layer is disposed in the through hole and covered by the protection layer.

Abstract: The present disclosure provides a carrying structure for carrying electronic device. The carrying structure comprises a carrying base, a start-up member, a linkage module, a latch member, a first buckle member, and a releasing member. When an electronic device is disposed to the carrying base, the electronic device drives the start-up member, which drives the latch member via the linkage module so that the latch member can fix the electronic device to the carrying base. To disassemble the electronic device from the carrying base, press the releasing member, which pushes the first buckle member and makes the latch member depart from the first buckle member and restore to the original position. Consequently, the start-up member and the linkage module can restore to the original positions. Thereby, the effects of rapid assembling and disassembling can be achieved.

Abstract: A chip package includes a packaging substrate, a semiconductor chip, and a plurality of conductive structures. The semiconductor chip has a central region and an edge region that surrounds the central region. The conductive structures are between the packaging substrate and the semiconductor chip. The conductive structures have different heights, and the heights of the conductive structures are gradually increased from the central region of the semiconductor chip to the edge region of the semiconductor chip, such that a distance between the edge region of the semiconductor chip and the packaging substrate is greater than a distance between the central region of the semiconductor chip and the packaging substrate.

Abstract: An embodiment of the disclosure provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed on the first surface and extending into the first recess and/or the second recess; an insulating layer located between the wire layer and the semiconductor substrate; a chip disposed on the first surface; and a conducting structure disposed between the chip and the first surface.

Abstract: A support bracket includes a housing, a driving member, a first linking member, a gear mechanism, a first engaging member, a second linking member and a second engaging member. The housing has a guiding rail and a through hole. The driving member has a driving portion and a first rack portion, and the driving portion is exposed out of the housing. The first linking member has a second rack portion and an engaging groove. The gear mechanism meshes with the first rack portion and the second rack portion. The first engaging member has a guiding portion and a first engaging portion, and the guiding portion is disposed in the guiding rail. Opposite ends of the second linking member are pivotally connected to the first linking member and the first engaging member, respectively. The second engaging member has a second engaging portion.

Abstract: An electronic device package and fabrication method thereof is provided. First, a semiconductor substrate is provided and the upper surface of it is etched to from recesses. A first isolation layer is formed on the upper surface and the sidewalls of the recesses. A conductive part is formed to fulfill the recesses and a conductive pad is formed on the first isolation layer to connect the conductive part. An electronic device is combined with the semiconductor substrate on the supper surface, wherein the electronic device has a connecting pad electrically connected to the conductive pad. The semiconductor substrate is thinned form its lower surface to expose the conductive part. A second isolation layer is formed below the lower surface and has an opening to expose the conductive part. A redistribution metal line is formed below the second isolation layer and in the opening to electrically connect to the conductive part.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

Abstract: A fabrication method of a chip package includes the following steps. A wafer structure having a wafer and a protection layer is provided. The first opening of the wafer is aligned with and communicated with the second opening of the protection layer. A first insulating layer having a first thickness is formed on a conductive pad exposed from the second opening, and a second insulating layer having a second thickness is formed on a first sidewall of the protection layer surrounding the second opening and a second sidewall of the wafer surrounding the first opening. The first and second insulating layers are etched, such that the first insulating layer is completely removed, and the second thickness of the second insulating layer is reduced.

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.

Abstract: A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.

Abstract: A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.

Abstract: An engagement structure for a cable head includes a main body and a release mechanism. The main body has movable positioners disposed thereon. When the cable head is inserted in the main body, the positioners are temporarily pushed away and moved back by an elastic mechanism to block the cable head from removing from the main body. For removing the cable head, a release mechanism is configured for pushing the positioners away. Thus, user can remove the cable head by operating the release mechanism. Therefore, operation of the engagement structure is simplified for user.

Abstract: An antitheft device includes a cover, a base plate, and an adhesive element. The base plate is located in a receiving space of the cover and is adapted for a controlling element to connect thereto to release or lock the cover and the base plate. The base plate is able to be adhered onto an object to be secured by the adhesive element. The adhesive element is also located in the receiving space of the cover so that the adhesive element is prevented from being removed or broken easily.

Abstract: A substrate structure with through vias is provided. The substrate structure with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the semiconductor substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers.