Abstract: A method for forming a floating gate electrode within a split gate field effect transistor device provides for isotropically processing a blanket isotropically processable material layer having a patterned mask layer formed thereover to form a patterned isotropically processed material layer which encroaches beneath the patterned mask layer. The patterned isotropically processed material layer may then be employed as a mask for forming a floating gate electrode from a blanket floating gate electrode material layer. The method provides for forming adjacent floating gate electrodes with less than minimally photolithographically resolvable separation.

Abstract: A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a “smiling” gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls of the trench. An exceptionally thin nitride layer overlying the first conformal oxide layer provides the necessary protection during the oxidation of the first polysilicon layer so as to prevent the “smiling” effect normally encountered in fabricating ultra large scale integrated circuits.

Abstract: A composite floating gate structure in flash memory cells is disclosed. Parallel active regions separated by isolation regions that extend from the surface of a semiconductor region of a substrate into the semiconductor region. A gate dielectric layer is disposed over the active regions. Planar parts of composite floating gates are composed of a first conductive layer and are equally spaced along the active regions where they are disposed over the gate dielectric layer. Spacer like parts of composite floating gates are composed of a second conductive layer and are disposed over the planar parts along both edges of edges planar parts so that sidewalls of the spacer like parts are parallel to the active regions. The spacer like parts and the planar parts compose the composite floating gates. An interlevel dielectric layer is patterned into equally spaced parallel stripes perpendicular to the active regions and each stripe is disposed over the corresponding composite floating gate for each active region.

Abstract: A finger-like floating gate structure in flash memory cells is disclosed. Raised isolation regions within a semiconductor region separate parallel active regions. A gate dielectric layer is disposed over the active regions. Finger-like floating gates are equally spaced along the active regions. The finger-like floating gates are comprised of a conductive base section that is disposed over the gate dielectric layer and three conductive finger sections that are in intimate electrical contact with the base section. An interlevel dielectric layer is patterned into equally spaced parallel stripes perpendicular to the active regions and each stripe is disposed over the corresponding composite floating gate for each active region. Word lines, which are composed of a third conductive layer, are parallel lines disposed over the interlevel dielectric layer and serve as control gates.

Abstract: A new method to form control gates and erase gates for split-gate flash memory cells is achieved. A unique flash device is achieved. The method comprises providing floating gates overlying a substrate. A control dielectric layer is formed overlying the floating gates and the substrate. A control conductor layer is formed overlying the control dielectric layer. Sidewall spacers are formed on the control conductor layer. The control conductor layer is partially etched down to create gaps between the sidewall spacers and the floating gates. The remaining control conductor layer forms control gates laterally adjacent to the floating gates. An isolating dielectric layer is formed overlying the control gates. An erase dielectric layer is formed lining the gaps and overlying the isolating dielectric layer. An erase conductor layer is deposited overlying the erase dielectric layer and isolating dielectric layer.

Abstract: A multi-bit split-gate (MSG) flash cell with multi-shared source/drain, a method of making and a method of programming the same are disclosed. Furthermore, a method of bit-by-bit erasing, in addition to page erasing, of a plurality of cells of two or more is disclosed through the application of a positive voltage forced onto the control gate of the unselected cell. Thus, by providing the bit-by-bit erasing flexibility, the bit alterability is enhanced. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. The programming, that is, writing of the plurality of N+1 bits is accomplished also bit by bit where the programmed bits are selected by word line, bit line and control gate. The read operation is similar to the write operation.

Abstract: A new method to form flash memory devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A first film is formed comprising a first oxide layer overlying the substrate and a floating gate layer overlying the first oxide layer. A second film is formed comprising a second oxide layer overlying the first film, a control gate layer overlying the second oxide layer, and an insulating layer overlying the control gate layer. The first and second films are patterned to form stacked gates comprising floating gates and control gates. Ions are implanted into the substrate between the stacked gates to form source and drain regions. A third oxide layer is then formed on the sidewalls of the stacked gates. A plug layer is then deposited overlying the substrate and the stacked gates and filling spaces between the stacked gates.

Abstract: A new method to form split gate flash memory cells in the manufacture of an integrated circuit device is achieved. The method comrpises providing a substrate. Pairs of floating gates are formed overlying the substrate. Common source plugs are formed overlying the substrate and filling spaces between the floating gate pairs. An oxide layer is formed overlying the substrate, the floating gates, and the common source plugs. A conductor layer is deposited overlying the oxide layer. First dielectric spacers are formed on vertical surfaces of the conductor layer. The conductor layer is etched through where not covered by the first dielectric spacers to thereby form word line gates adjacent to the floating gates. Second dielectric spacers are formed on vertical surfaces of the word line gates and the first dielectric spacers to complete the split gate flash memory cells.

Abstract: A stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling is described. An unconventionally high isolation oxide layer is formed in a shallow trench isolation (STI) in a substrate. The deep opening in the space between the STIs is conformally lined with a polysilicon to form a floating gate extending above the opening. A conformal intergate oxide lines the entire floating gate. A layer of polysilicon overlays the intergate oxide and protrudes downward into the openings to form a control gate with increased coupling to the floating gate.

Abstract: A new split gate structure is disclosed with improved programming efficiency. A silicon region, extending to the surface of a semiconductor substrate, has parallel source/drain regions and electrical connecting regions disposed over the source/drain region. A multiplicity of structures is situated between source drain regions. Each structure is composed of two tower structures and intervening oxide layers. A floating gate tower, in which a gate oxide layer separates a floating gate from said silicon region and an insulating layer separates said floating gate from a top gate, with a nitride layer disposed over the top gate. And a selected gate tower in which a silicon pedestal is in intimate electrical contact with said silicon region and said silicon pedestal is separated from a selected gate by an insulating layer.

Abstract: A new structure is disclosed for semiconductor devices in which contact regions are self-aligned to conductive lines. Openings to a gate oxide layer, in partially fabricated devices on a silicon substrate, have insulating sidewalls. First polysilicon lines disposed against the insulating sidewalls extend from below the top of the openings to the gate oxide layer. Oxide layers are grown over the top and exposed sides of the first polysilicon lines serving to insulate the first polysilicon lines. Polysilicon contact regions are disposed directly over and connect to silicon substrate regions through openings in the gate oxide layer and fill the available volume of the openings. Second polysilicon lines connect to the contact regions and are disposed over the oxide layers grown on the first polysilicon lines.

Abstract: A structure is disclosed to improve the coupling ratio of top gate to floating gate in flash memory cells. Parallel active regions are surrounded by isolation regions and are disposed over a semiconductor region of a substrate. The isolation regions have a portion within and a portion above the semiconductor region. The semiconductor region under the active regions is doped in the vicinity of the surface to adjust the threshold voltage. Insulator spacers are disposed against the sidewalls of the portion of the isolation regions that are above the semiconductor region and they taper so they are wider near the semiconductor region, and thus the spacing between neighboring insulator spacers on the same active region decreases closer to the semiconductor region. Conductive floating gates spaced along the active regions are separated from the semiconductor region by a floating gate insulator layer, are disposed between insulator spacers and extend about to the height of the isolation regions.

Abstract: A split-gate flash memory cell having improved programming and erasing speed with a tilted trench source, and also a method of forming the same are provided. This is accomplished by forming two floating gates and their respective control gates sharing a common source region. A trench is formed in the source region and the walls are sloped to have a tilt. A source implant is performed at a tilt angle and the trench is lined with a gate oxide layer. Subsequently, a lateral diffusion of the source implant is performed followed by thermal cycling. The lateral enlargement of the diffused source is found to increase the coupling ratio of the split-gate flash memory cell substantially.

Abstract: A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floating gate and control gate, respectively, of the split-gate flash memory cell. Furthermore, the thin interpoly oxide of the cell, rather than the thick poly-oxide over the floating gate is used as the insulator between the plates of the capacitor. The resulting capacitor yields high storage capacity through high capacitance per unit area.

Abstract: A method is provided for forming a short and sharp gate bird's beak in order to increase the erase speed of a split-gate flash memory. This is accomplished in two embodiments where in the first, fluorine is implanted in the first polysilicon layer to form the floating gate. It is disclosed here that the implanting of fluorine increases the oxidation rate of the polysilicon and because of the faster oxidation, the polygate bird's beak that is formed attains a relatively short and sharp in comparison with conventional beaks. This has the attendant benefit of forming a relatively small memory cell, and the concomitant reduction in the erase speed of the cell. In the second embodiment, oxygen is used with the same favorable results. A third embodiment discloses the structure of a split-gate flash memory cell having a sharp bird's beak.

Abstract: A new split gate structure is disclosed with improved programming efficiency. A silicon region, extending to the surface of a semiconductor substrate, has parallel source/drain regions and electrical connecting regions disposed over the source/drain region. A multiplicity of structures is situated between source drain regions. Each structure is composed of two tower structures and intervening oxide layers. A floating gate tower, in which a gate oxide layer separates a floating gate from said silicon region and an insulating layer separates said floating gate from a top gate, with a nitride layer disposed over the top gate. And a selected gate tower in which a silicon pedestal is in intimate electrical contact with said silicon region and said silicon pedestal is separated from a selected gate by an insulating layer.

Abstract: A new method to form flash memory devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A first film is formed comprising a first oxide layer overlying the substrate and a floating gate layer overlying the first oxide layer. A second film is formed comprising a second oxide layer overlying the first film, a control gate layer overlying the second oxide layer, and an insulating layer overlying the control gate layer. The first and second films are patterned to form stacked gates comprising floating gates and control gates. Ions are implanted into the substrate between the stacked gates to form source and drain regions. A third oxide layer is then formed on the sidewalls of the stacked gates. A plug layer is then deposited overlying the substrate and the stacked gates and filling spaces between the stacked gates.

Abstract: A multi-bit split-gate (MSG) flash cell with multi-shared source/drain, a method of making and a method of programming the same are disclosed. Furthermore, a method of bit-by-bit erasing, in addition to page erasing, of a plurality of cells of two or more is disclosed through the application of a positive voltage forced onto the control gate of the unselected cell. Thus, by providing the bit-by-bit erasing flexibility, the bit alterability is enhanced. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. The programming, that is, writing of the plurality of N+1 bits is accomplished also bit by bit where the programmed bits are selected by word line, bit line and control gate. The read operation is similar to the write operation.

Abstract: A new structure is disclosed for source/drain bit lines in arrays of MOSFET devices. Rows of conducting regions are formed by ion implantation through openings adjacent to gate structures and in isolation regions separating columns of active areas of the arrays. The openings are filled with insulating material.

Abstract: A multi-bit split-gate (MSG) flash cell with multi-shared source/drain, a method of making and a method of, programming the same are disclosed. Furthermore, a method of single bit erasing combined with block erasing of a plurality of cells of two or more is disclosed through the application of a negative voltage forced onto the control gate of the selected cell. Thus, by providing the single bit erasing flexibility, the bit alterability is enhanced. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. The programming, that is, writing of the plurality of N+1 bits is accomplished also bit by bit where the programmed bits are selected by word line, bit line and control gate. The read operation is similar to the write operation.