Abstract: A new structure is disclosed for semiconductor devices in which contact regions are self-aligned to conductive lines. Openings to a gate oxide layer, in partially fabricated devices on a silicon substrate, have insulating sidewalls. First polysilicon lines disposed against the insulating sidewalls extend from below the top of the openings to the gate oxide layer. Oxide layers are grown over the top and exposed sides of the first polysilicon lines serving to insulate the first polysilicon lines. Polysilicon contact regions are disposed directly over and connect to silicon substrate regions through openings in the gate oxide layer and fill the available volume of the openings. Second polysilicon lines connect to the contact regions and are disposed over the oxide layers grown on the first polysilicon lines.

Abstract: A self-aligned conductive region to active region structure is disclosed in which parallel active regions of a semiconductor region of a substrate, which extends to a surface, are separated by STI regions. The STI regions have an insulator liner layer grown over their sides and are filled with an insulator filler layer. Equally spaced gate insulator regions, formed prior to the STI regions, are disposed over the active regions and overlap a portion of the insulator liner layer. Conductive regions, formed prior to the STI regions, are disposed over the gate insulator regions.

Abstract: A multi-bit split-gate (MSG) flash cell with multi-shared source/drain and making of the same are disclosed. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. With the disclosed MSG, a multiplicity of N+1 bit programming can be accomplished bit by bit where the programmed bits are selected by word line, bit line and control gate. In the erase operation, erased bits are selected by word line, while in the read operation, operations similar to write operation are performed. Thus, it is disclosed here that a plurality of N+1 bits or cells, where N is any integer, can be formed between two bit lines and along the same word line.

Abstract: A finger-like floating gate structure in flash memory cells is disclosed. Raised isolation regions within a semiconductor region separate parallel active regions. A gate dielectric layer is disposed over the active regions. Finger-like floating gates are equally spaced along the active regions. The finger-like floating gates are comprised of a conductive base section that is disposed over the gate dielectric layer and three conductive finger sections that are in intimate electrical contact with the base section. An interlevel dielectric layer is patterned into equally spaced parallel stripes perpendicular to the active regions and each stripe is disposed over the corresponding composite floating gate for each active region. Word lines, which are composed of a third conductive layer, are parallel lines disposed over the interlevel dielectric layer and serve as control gates.

Abstract: A structure is disclosed for split-gate flash memory cells in which isolation regions separate parallel active regions within a semiconductor region. Trapezoidal floating gates, separated from the active regions by an insulator layer, are equally spaced over the active regions. Three tiered parallel strips run perpendicular to the active regions and pass over corresponding trapezoidal floating gates, the bottom and top tiers being insulator layers and the middle tier being a conductor layer. Insulator spacers are disposed over the sidewalls of the three-tiered parallel strips and of the trapezoidal floating gates. These parallel structures are designated floating gate towers. Source/drain regions are formed in the semiconductor region of every other opening between floating gate towers where they are contacted by source/drain contact lines. An insulator layer is disposed over the source/drain contact lines.

Abstract: A split-gate flash memory device. The device comprises a floating gate, a control gate, and an erase gate. The floating gate is overlying a substrate. The control gate is laterally adjacent to the floating gate and overlying the substrate. The erase gate is laterally adjacent to the floating gate and overlying the control gate, in which the erase gate is between a sidewall spacer and the floating gate.

Abstract: A multi-bit split-gate (MSG) flash cell with multi-shared source/drain and making of the same are disclosed. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. With the disclosed MSG, a multiplicity of N+1 bit programming can be accomplished bit by bit where the programmed bits are selected by word line, bit line and control gate. In the erase operation, erased bits are selected by word line, while in the read operation, operations similar to write operation are performed. Thus, it is disclosed here that a plurality of N+1 bits or cells, where N is any integer, can be formed between two bit lines and along the same word line.

Abstract: A split gate structure is disclosed for improved programming and erasing efficiency. Source/drain regions are equally spaced along the active regions and are electrically connected by source/drain towers that run perpendicular to the active regions. Floating gate towers are situated between each pair of source/drain towers. A floating gate tower has insulating layers separating floating gates, which exist only over active regions crossed by the floating gate tower, from a semiconductor region. An insulating layer separates the floating gates from a top gate and an insulating layer is disposed over the top gate. Insulator spacers are disposed over the sidewalls. Programming injectors, in electrical contact with the semiconductor region, are disposed against the sidewalls of the floating gate towers except where there are source/drain towers and taper to a sharp edge at a height so that they face the floating gates. Selected gates are disposed over the active regions.

Abstract: A split-gate flash memory cell having improved programming and erasing speed with a tilted trench source, and also a method of forming the same are provided. This is accomplished by forming two floating gates and their respective control gates sharing a common source region. A trench is formed in the source region and the walls are sloped to have a tilt. A source implant is performed at a tilt angle and the trench is lined with a gate oxide layer. Subsequently, a lateral diffusion of the source implant is performed followed by thermal cycling. The lateral enlargement of the diffused source is found to increase the coupling ratio of the split-gate flash memory cell substantially.

Abstract: Within a stacked gate field effect transistor (FET) device, as well as a method for fabrication thereof and a method for operation thereof, there is provided a stacked gate field effect transistor (FET) device comprising a layered stack of a tunneling dielectric layer, a floating gate electrode, an inter-gate electrode dielectric layer and a control gate electrode formed upon a semiconductor substrate. To enhance performance of the stacked gate field effect transistor (FET) device, at least one of: (1) the floating gate electrode is formed with a pointed edge tip at its outer sidewall; (2) the floating gate electrode in formed with a pointed linear recess centered within its linewidth; and (3) a pair of source/drain regions is formed asymmetrically penetrating beneath the pair of opposite edges of the floating gate electrode and not laterally spaced from a floating gate electrode sidewall.

Abstract: A new structure is disclosed for semiconductor devices in which contact regions are self-aligned to conductive lines. Openings to a gate oxide layer, in partially fabricated devices on a silicon substrate, have insulating sidewalls. First polysilicon lines disposed against the insulating sidewalls extend from below the top of the openings to the gate oxide layer. Oxide layers are grown over the top and exposed sides of the first polysilicon lines serving to insulate the first polysilicon lines. Polysilicon contact regions are disposed directly over and connect to silicon substrate regions through openings in the gate oxide layer and fill the available volume of the openings. Second polysilicon lines connect to the contact regions and are disposed over the oxide layers grown on the first polysilicon lines.

Abstract: A new method to form split gate flash memory cells in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. Pairs of floating gates are formed overlying the substrate. Common source plugs are formed overlying the substrate and filling spaces between the floating gate pairs. An oxide layer is formed overlying the substrate, the floating gates, and the common source plugs. A conductor layer is deposited overlying the oxide layer. First dielectric spacers are formed on vertical surfaces of the conductor layer. The conductor layer is etched through where not covered by the first dielectric spacers to thereby form word line gates adjacent to the floating gates. Second dielectric spacers are formed on vertical surfaces of the word line gates and the first dielectric spacers to complete the split gate flash memory cells.

Abstract: A new method to form control gates and erase gates for split-gate flash memory cells is achieved. A unique flash device is achieved. First, floating gates are provided overlying a substrate. A control dielectric layer is formed overlying the floating gates and the substrate. A control conductor layer is formed overlying the control dielectric layer. Sidewall spacers are formed on the control conductor layer. The control conductor layer is partially etched down to create gaps between the sidewall spacers and the floating gates. The remaining control conductor layer forms control gates laterally adjacent to the floating gates. An isolating dielectric layer is formed overlying the control gates. An erase dielectric layer is formed lining the gaps and overlying the isolating dielectric layer. An erase conductor layer is deposited overlying the erase dielectric layer and isolating dielectric layer.

Abstract: A finger-like floating gate structure in flash memory cells is disclosed. Raised isolation regions within a semiconductor region separate parallel active regions. A gate dielectric layer is disposed over the active regions. Finger-like floating gates are equally spaced along the active regions. The finger-like floating gates are comprised of a conductive base section that is disposed over the gate dielectric layer and three conductive finger sections that are in intimate electrical contact with the base section. An interlevel dielectric layer is patterned into equally spaced parallel stripes perpendicular to the active regions and each stripe is disposed over the corresponding composite floating gate for each active region. Word lines, which are composed of a third conductive layer, are parallel lines disposed over the interlevel dielectric layer and serve as control gates.

Abstract: A method for forming a floating gate electrode within a split gate field effect transistor device provides for isotropically processing a blanket isotropically processable material layer having a patterned mask layer formed thereover to form a patterned isotropically processed material layer which encroaches beneath the patterned mask layer. The patterned isotropically processed material layer may then be employed as a mask for forming a floating gate electrode from a blanket floating gate electrode material layer. The method provides for forming adjacent floating gate electrodes with less than minimally photolithographically resolvable separation.

Abstract: A split gate structure is disclosed for improved programming and erasing efficiency. A semiconductor region extending to the surface of a substrate has isolation regions surrounding parallel active regions. Source/drain regions in the semiconductor region are equally spaced along the active regions and are electrically connected by source/drain connecting regions, denoted source/drain towers, disposed over said source/drain regions and running perpendicular to the active regions. A multiplicity of structures denoted floating gate towers, parallel to the source/drain towers are situated between each pair of said source/drain towers. A floating gate tower having first insulating layers, disposed over the semiconductor region within the active regions crossed by the floating gate tower, separating floating gates, which exist only over active regions crossed by the floating gate tower, from the semiconductor region.

Abstract: A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a “smiling” gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls of the trench. An exceptionally thin nitride layer overlying the first conformal oxide layer provides the necessary protection during the oxidation of the first polysilicon layer so as to prevent the “smiling” effect normally encountered in fabricating ultra large scale integrated circuits.

Abstract: A finger-like floating gate structure in flash memory cells is disclosed. Raised isolation regions within a semiconductor region separate parallel active regions. A gate dielectric layer is disposed over the active regions. Finger-like floating gates are equally spaced along the active regions. The finger-like floating gates are comprised of a conductive base section that is disposed over the gate dielectric layer and three conductive finger sections that are in intimate electrical contact with the base section. An interlevel dielectric layer is patterned into equally spaced parallel stripes perpendicular to the active regions and each stripe is disposed over the corresponding composite floating gate for each active region. Word lines, which are composed of a third conductive layer, are parallel lines disposed over the interlevel dielectric layer and serve as control gates.

Abstract: A composite floating gate structure in flash memory cells is disclosed. Parallel active regions separated by isolation regions that extend from the surface of a semiconductor region of a substrate into the semiconductor region. A gate dielectric layer is disposed over the active regions. Planar parts of composite floating gates are composed of a first conductive layer and are equally spaced along the active regions where they are disposed over the gate dielectric layer. Spacer like parts of composite floating gates are composed of a second conductive layer and are disposed over the planar parts along both edges of edges planar parts so that sidewalls of the spacer like parts are parallel to the active regions. The spacer like parts and the planar parts compose the composite floating gates. An interlevel dielectric layer is patterned into equally spaced parallel stripes perpendicular to the active regions and each stripe is disposed over the corresponding composite floating gate for each active region.

Abstract: A multi-bit split-gate (MSG) flash cell with multi-shared source/drain, a method of making and a method of programming the same are disclosed. Furthermore, a method of bit-by-bit erasing, in addition to page erasing, of a plurality of cells of two or more is disclosed through the application of a positive voltage forced onto the control gate of the unselected cell. Thus, by providing the bit-by-bit erasing flexibility, the bit alterability is enhanced. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. The programming, that is, writing of the plurality of N+1 bits is accomplished also bit by bit where the programmed bits are selected by word line, bit line and control gate. The read operation is similar to the write operation.