Abstract: A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complementary word line. The first and second CMOS devices are complementary to one another. An output node is coupled between the first CMOS device and the second CMOS device. A method of programming a non-volatile field programmable gate array (NV-FPGA) includes coupling an information handling system to the FPGA, performing a block erase of a plurality of memory cells in the FPGA, verifying that the block erase is successful, programming an upper page of the FPGA, verifying that the upper page programming is successful, programming a lower page of the FPGA and verifying that the lower page programming is successful.

Abstract: The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings.

Abstract: Provided is a method of fabricating a memory device. A substrate including an array region and a peripheral region is provided. A first feature and a second feature are formed in the array region. The first feature and the second feature have a first pitch. A plurality of spacers abutting each of the first feature and the second feature are formed. The plurality of spacers have a second pitch. A third feature in the peripheral region and a fourth and fifth feature in the array region are formed concurrently. The forth and fifth feature have the second pitch.

Abstract: A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased.

Abstract: A 2-transistor (2T) memory cell comprising a first transistor and a second transistor. The first and second transistors respectively have a source and a drain separated apart by a channel thereof, a floating gate over the channel near the source side, and a control gate over the floating gate and the channel near the drain side. The sources, floating gates, and control gates of the first and second transistors are respectively mutually connected. In addition, driving capability of the second transistor is substantially larger than that of the first transistor.

Abstract: A method of making embedded non-volatile memory devices includes forming a first mask layer overlying a polycrystalline silicon layer in a cell region and a peripheral region on a semiconductor substrate wherein the first mask layer has a plurality of openings in the cell region. Portions of the polycrystalline silicon layer exposed in the plurality of openings can be oxidized to form a plurality of poly-oxide regions, and the first mask layer can then be removed. The polycrystalline silicon layer not covered by the plurality of poly-oxide regions can be etched to form a plurality of floating gates, wherein etching the polycrystalline silicon layer is accompanied by a sputtering. A dielectric layer can then be formed, as well as a second mask layer in both the cell region and the peripheral region. The second mask layer in the cell region is partially etched back after a photoresist layer is formed over the second mask layer in the peripheral region.

Abstract: A structure is disclosed to improve the coupling ratio of top gate to floating gate in flash memory cells. Parallel active regions are surrounded by isolation regions and are disposed over a semiconductor region of a substrate. The isolation regions have a portion within and a portion above the semiconductor region. The semiconductor region under the active regions is doped in the vicinity of the surface to adjust the threshold voltage Insulator spacers are disposed against the sidewalls of the portion of the isolation regions that are above the semiconductor region and they taper so they are wider near the semiconductor region, and the spacing between neighboring insulator spacers on the same active region decreases closer to the semiconductor region Conductive floating gates spaced along the active regions are separated from the semiconductor region by a floating gate insulator layer, are disposed between insulator spacers and extend about to the height of the isolation regions.

Abstract: A new structure is disclosed for semiconductor devices with which contact regions are self-aligned to conductive lines. Openings to a gate oxide layer, in partially fabricated devices on a silicon substrate, having insulating sidewalls. First polysilicon lines disposed against the insulating sidewalls extend from below the top of the openings to the gate oxide layer. Oxide layers are grown over the top and exposed sides of the first polysilicon lines serving to insulate the first polysilicon lines. Polysilicon contact regions are disposed directly over and connect to silicon substrate regions through openings in the gate oxide layer and fill the available volume of the openings. Second polysilicon lines connect to the contact regions and are disposed over the oxide layers grown on the first polysilicon lines.

Abstract: A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.

Abstract: A split-gate, P-channel flash memory cell having a band-to-band hot electron (BBHE) programming method is defined to improve the endurance characteristics of performance of the cell. The split-gate, P-channel structure, which includes a P+ drain, P+ source, floating gate and a control gate, advantageously improves protection from over-erase and hot-hole trap conditions, and improves programming speed and higher injection efficiency. The cell is erased by a polysilicon-polysilicon tunneling technique.

Abstract: A structure for flash memory cells is disclosed, Isolation regions are formed in a semiconductor region separating cells and also separating programming bit line channel regions of a cell from reading bit line charmel regions of a cell. A conductive floating gates has a first portion in the programming bit line channel region of a cell and a second portion in the reading bit line channel region of the cell and a third connecting portion passing over an isolation region.

Abstract: A method of making embedded non-volatile memory devices includes forming a first mask layer overlying a polycrystalline silicon layer in a cell region and a peripheral region on a semiconductor substrate wherein the first mask layer has a plurality of openings in the cell region. Portions of the polycrystalline silicon layer exposed in the plurality of openings can be oxidized to form a plurality of poly-oxide regions, and the first mask layer can then be removed. The polycrystalline silicon layer not covered by the plurality of poly-oxide regions can be etched to form a plurality of floating gates, wherein etching the polycrystalline silicon layer is accompanied by a sputtering. A dielectric layer can then be formed, as well as a second mask layer in both the cell region and the peripheral region. The second mask layer in the cell region is partially etched back after a photoresist layer is formed over the second mask layer in the peripheral region.

Abstract: A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.

Abstract: A self-aligned conductive region to active region structure is disclosed in which parallel active regions of a semiconductor region of a substrate, which extends to a surface, are separated by STI regions. The STI regions have an insulator liner layer grown over their sides and are filled with an insulator filler layer. Equally spaced gate insulator regions, formed prior to the STI regions, are disposed over the active regions and overlap a portion of the insulator liner layer. Conductive regions, formed prior to the STI regions, are disposed over the gate insulator regions.

Abstract: A new method to form MOS gates in an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a substrate. A polysilicon layer is formed overlying the dielectric layer. A patterned masking layer with an opening is formed overlying the polysilicon layer. Through the opening, the polysilicon layer is oxidized to form a first silicon oxide layer at the bottom of the opening. Thereafter the masking layer is removed and the polysilicon layer is exposed. The exposed polysilicon layer is then etched through using the first silicon oxide layer as a mask to form MOS floating gates. The first silicon oxide layer is then removed. A second conductor layer is then deposited overlying the MOS floating gates for forming control gates.

Abstract: A structure is disclosed to improve the coupling ratio of top gate to floating gate in flash memory cells. Parallel active regions are surrounded by isolation regions and are disposed over a semiconductor region of a substrate. The isolation regions have a portion within and a portion above the semiconductor region. The semiconductor region under the active regions is doped in the vicinity of the surface to adjust the threshold voltage Insulator spacers are disposed against the sidewalls of the portion of the isolation regions that are above the semiconductor region and they taper so they are wider near the semiconductor region, and thus the spacing between neighboring insulator spacers on the same active region decreases closer to the semiconductor region Conductive floating gates spaced along the active regions are separated from the semiconductor region by a floating gate insulator layer, are disposed between insulator spacers and extend about to the height of the isolation regions.

Abstract: A method of forming a semiconductor device comprises forming a gate dielectric layer and a gate electrode over the gate dielectric layer on a semiconductor substrate, partially removing the gate dielectric layer to form two recesses separated by the gate dielectric layer and disposed substantially under the gate electrode, and substantially filling the two recesses with an oxide layer and a material layer to form two separated regions operable to each hold an electrical charge.

Abstract: A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased.

Abstract: A split-gate flash memory device. The device includes a floating gate, a control gate, and an erase gate. The floating gate is overlying a substrate. The control gate is laterally adjacent to the floating gate and overlying the substrate. The erase gate is laterally adjacent to the floating gate and overlying the control gate, in which the erase gate is between a sidewall spacer and the floating gate.

Abstract: A new structure is disclosed for semiconductor devices in which contact regions are self-aligned to conductive lines. Openings to a gate oxide layer, in partially fabricated devices on a silicon substrate, have insulating sidewalls. First polysilicon lines disposed against the insulating sidewalls extend from below the top of the openings to the gate oxide layer. Oxide layers are grown over the top and exposed sides of the first polysilicon lines serving to insulate the first polysilicon lines. Polysilicon contact regions are disposed directly over and connect to silicon substrate regions through openings in the gate oxide layer and fill the available volume of the openings. Second polysilicon lines connect to the contact regions and are disposed over the oxide layers grown on the first polysilicon lines.