Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate. The chip structure has an inclined sidewall, the inclined sidewall is at an acute angle to a vertical, the vertical is a direction perpendicular to a main surface of the chip structure, and the acute angle is in a range from about 12 degrees to about 45 degrees. The method also includes forming a protective layer to surround the chip structure.

Abstract: A transparent conductive film comprises a substrate, a metal nanowire layer disposed on the substrate, and a water blocking protective layer, which has water absorbing particles and is disposed on the metal nanowire layer. The transparent conductive film has a first absorption peak in a 2750 cm?1 to 3000 cm?1 wavenumber region and a second absorption peak in a 3000 cm?1 to 3750 cm?1 wavenumber region using FTIR detection. A ratio of a maximum peak intensity of the second absorption peak to a maximum peak intensity of the first absorption peak ranges from 0.18 to 0.50, and a haze value of the transparent conductive film is 1.7% or less. The transparent conductive film can overcome the problems of poor bending resistance and visibility and can be appropriately applied to touch sensors due to bendability and high water blocking performance of the transparent conductive film.

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: An electronic package is provided, in which electronic elements and at least one packaging module including a semiconductor chip and a shielding structure covering the semiconductor chip are disposed on a carrier structure, an encapsulation layer encapsulates the electronic elements and the packaging module, and a shielding layer is formed on the encapsulation layer and in contact with the shielding structure. Therefore, the packaging module includes the semiconductor chip and the shielding structure and has a chip function and a shielding wall function simultaneously.

Abstract: A computer system receives, by a first application, a plurality of shared media items. After receiving the plurality of shared media items, the computer system receives, via one or more input devices, a request to search a media library of a second application that is different from the first application for media items in the media library that meet search criteria. In response to receiving the request to search the media library, the computer system concurrently displays, via a display generation component, two or more media items that meet the search criteria. The two or more media items include: one or more media items from the media library of the second application that meet the search criteria, and one or more of the shared media items that are not stored within the media library of the second application and that meet the search criteria.

Abstract: Embodiments utilize a two layer inner spacer structure during formation of the inner spacers of a nano-FET device. The materials of the first inner spacer layer and second inner spacer layer can be selected to have a mismatch in their coefficients of thermal expansion (CTE). As the structure cools after deposition, the inner spacer layer which has a larger CTE will exhibit compressive stress on the other inner spacer layer, however, because the two layers have a common interface, the layer with the smaller CTE will exhibit a counter acting tensile stress.

Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.

Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.

Abstract: Antigen binding molecules (ABMs) comprising Fab domains in non-native configurations, ABM conjugates comprising the ABMs and cytotoxic or cytostatic agents, pharmaceutical compositions containing the ABMs and ABM conjugates, methods of using the ABMs, ABM conjugates and pharmaceutical compositions for treating cancer, nucleic acids encoding the ABMs, cells engineered to express the ABMs, and methods of producing ABMs.

Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.

Abstract: This invention relates to a clamp with elastic opening function, which includes at least a first clamping body and a second clamping body. Said first clamping body is provided with a first clamping portion and a first axle seat, said second clamping body is provided with a second clamping portion and a second axle seat, said first clamping portion and second clamping portion are arranged in correspondence with each other. Said first axle seat and second axle seat are pivotally connected to each other through a pivot, so that said first clamping body and second clamping body can rotate relatively. The upper end of said first axle seat is provided with a first pressing portion, and the lower end of said second axle seat is provided with a second pressing portion, a spiral clutch device and an elastic telescopic torsion member are arranged between said first axle seat and second axle seat.

Abstract: A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Abstract: The present invention provides multispecific antigen-binding molecules that bind both a T-cell antigen (e.g., CD3) and a target antigen (e.g., a tumor associated antigen, a viral or bacterial antigen), and which include a single polypeptide chain that is multivalent (e.g., bivalent) with respect to T-cell antigen binding, and uses thereof.

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

Abstract: A method includes providing a fin extending from a substrate, the fin including a plurality of semiconductor channel layers, and where a gate is disposed over the fin. A first spacer layer is deposited over the gate and over the fin in a source/drain region. The first spacer layer has a first etch rate. A second spacer layer is deposited over the first spacer layer. The second spacer layer has a second etch rate less than the first etch rate. The plurality of semiconductor channel layers are removed from the source/drain region to form a trench having a funnel shape. After forming the trench, inner spacers are formed along a sidewall surface of the trench. In various embodiments, lateral sidewall surfaces of each semiconductor channel layer of the plurality of semiconductor channel layers is substantially free of an inner spacer material.

Abstract: A method for automatically setting addresses suitable for an RS485 system is provided. The RS485 system includes a host device and a plurality of slave devices. The method includes the following stages. The host device confirms that there are no addresses of the slave devices in a database. The slave devices are turned on in sequence. The slave devices calculate their own respective power-on times. The slave device enter an idle state during the period associated with the power-on time. Only one of the slave devices sends the power-on time to the host device when said slave device leaves the idle state. The host device sets the address of said slave device according to the power-on time when said slave device leaves the idle state.

Abstract: The present disclosure provides interferon receptor agonists with improved safety profiles and therapeutic indices. The interferon receptor agonists are attenuated through masking and/or reduced receptor binding as compared to a wild-type interferon. IFN receptor agonists optionally further comprise a targeting moiety, e.g., a targeting moiety that recognizes a tumor- or immune cell-associated antigen and directs the interferon receptor agonist to a tumor site and/or tumor-reactive immune cells. The disclosure further provides pharmaceutical compositions comprising the interferon receptor agonists, and methods of use of the interferon receptor agonists in therapy, as well as nucleic acids encoding the interferon receptor agonists, recombinant cells that express the interferon receptor agonists and methods of producing the interferon receptor agonists.

Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a gate trench over a semiconductor channel, the gate trench being surrounded by gate spacers. The method includes sequentially depositing a work function metal, a glue metal, and an electrode metal in the gate trench. The method includes etching respective portions of the electrode metal and the glue metal to form a gate electrode above a metal gate structure. The metal gate structure includes a remaining portion of the work function metal and the gate electrode includes a remaining portion of the electrode metal. The gate electrode has an upper surface extending away from a top surface of the metal gate structure.

Abstract: A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.