Abstract: A method for automatically setting addresses suitable for an RS485 system is provided. The RS485 system includes a host device and a plurality of slave devices. The method includes the following stages. The host device confirms that there are no addresses of the slave devices in a database. The slave devices are turned on in sequence. The slave devices calculate their own respective power-on times. The slave device enter an idle state during the period associated with the power-on time. Only one of the slave devices sends the power-on time to the host device when said slave device leaves the idle state. The host device sets the address of said slave device according to the power-on time when said slave device leaves the idle state.

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

Abstract: A method includes providing a fin extending from a substrate, the fin including a plurality of semiconductor channel layers, and where a gate is disposed over the fin. A first spacer layer is deposited over the gate and over the fin in a source/drain region. The first spacer layer has a first etch rate. A second spacer layer is deposited over the first spacer layer. The second spacer layer has a second etch rate less than the first etch rate. The plurality of semiconductor channel layers are removed from the source/drain region to form a trench having a funnel shape. After forming the trench, inner spacers are formed along a sidewall surface of the trench. In various embodiments, lateral sidewall surfaces of each semiconductor channel layer of the plurality of semiconductor channel layers is substantially free of an inner spacer material.

Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a gate trench over a semiconductor channel, the gate trench being surrounded by gate spacers. The method includes sequentially depositing a work function metal, a glue metal, and an electrode metal in the gate trench. The method includes etching respective portions of the electrode metal and the glue metal to form a gate electrode above a metal gate structure. The metal gate structure includes a remaining portion of the work function metal and the gate electrode includes a remaining portion of the electrode metal. The gate electrode has an upper surface extending away from a top surface of the metal gate structure.

Abstract: The present disclosure provides interferon receptor agonists with improved safety profiles and therapeutic indices. The interferon receptor agonists are attenuated through masking and/or reduced receptor binding as compared to a wild-type interferon. IFN receptor agonists optionally further comprise a targeting moiety, e.g., a targeting moiety that recognizes a tumor- or immune cell-associated antigen and directs the interferon receptor agonist to a tumor site and/or tumor-reactive immune cells. The disclosure further provides pharmaceutical compositions comprising the interferon receptor agonists, and methods of use of the interferon receptor agonists in therapy, as well as nucleic acids encoding the interferon receptor agonists, recombinant cells that express the interferon receptor agonists and methods of producing the interferon receptor agonists.

Abstract: A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.

Abstract: An optical fiber module is provided and includes an optical fiber structure, a light-absorbing area and a photoelectric sensor in a housing. The optical fiber structure collectively arranges a plurality of first optical fibers to form at least one optical fiber bundle with a tapered end, and a second optical fiber is connected to the tapered end of the optical fiber bundle to converge the optical fiber bundle to the second optical fiber. The light-absorbing area corresponds to an end of the second optical fiber, such that the light-absorbing area absorbs scattering signals escaped and scattered when signals are transmitted from the plurality of first optical fibers to the second optical fiber. The photoelectric sensor is arranged corresponding to the plurality of first optical fibers to receive target signals escaped and refracted when the signals are transmitted from the second optical fiber to the plurality of first optical fibers.

Abstract: A semiconductor-on-insulator (SOI) structure and a method for forming the SOI structure. The method includes forming a first dielectric layer on a first semiconductor layer. A second semiconductor layer is formed over an etch stop layer. A cleaning solution is provided to a first surface of the first dielectric layer. The first dielectric layer is bonded under the second semiconductor layer in an environment having a substantially low pressure. An index guiding layer may be formed over the second semiconductor layer. A third semiconductor layer is formed over the second semiconductor layer. A distance between a top of the third semiconductor layer and a bottom of the second semiconductor layer varies between a maximum distance and a minimum distance. A planarization process is performed on the third semiconductor layer to reduce the maximum distance.

Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: An augmented reality interactive rehabilitation system includes an augmented reality eyewear device, a holding seat, a haptic module and sensing modules. The holding seat has a first recess and a second recess smaller in cross section than the first recess. The haptic module is removably placeable into the holding seat, and has a first end to be received in the first recess and a second end to be received in the second recess. The sensing modules are informationally connected to the augmented reality eyewear device and disposed in the holding seat to detect whether the haptic module is placed in a correct position.

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

Abstract: a resistance adjustable power generator having: an operating unit that receives commands of a user and is able to switch the resistance adjustable power generator to either a release mode or a resistance mode; a resistance generating unit that receive the commands from the operating unit and provides adjustable multiple levels of resistance to a connecting device, with the resistance generating unit having a resistance controlling center, multiple resistance generator, and an output controlling center; and a battery electrically connects to the resistance generating unit.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: Aspects of the disclosure provide a method. The method includes forming a structure over a substrate, and forming a spacer layer on the structure, wherein the spacer layer has a recess. The method includes forming a mask layer over the spacer layer and in the recess, the mask layer including a first layer, a second layer and a third layer. The method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and. The method includes removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

Abstract: A method for assessing drug-resistant Klebsiella pneumoniae includes the following steps. A test sample is provided, wherein the test sample includes a Klebsiella pneumoniae. A spectrum analysis step is performed, wherein the test sample is detected by a mass spectrometry method so as to obtain a target mass spectrum data. An assessing step for drug-resistant Klebsiella pneumoniae is performed, wherein the target mass spectrum data is analyzed so as to assess whether the Klebsiella pneumoniae is resistant to a carbapenem antibiotic or a colistin or not. When the Klebsiella pneumoniae is resistant to the carbapenem antibiotic, the target mass spectrum data includes a first anti-carbapenem feature mark, and when the Klebsiella pneumoniae is resistant to the colistin, the target mass spectrum data includes a first anti-colistin feature mark.