Abstract: In a method for inspecting pattern defects, a plurality of patterns are formed over an underlying layer. The plurality of patterns are electrically isolated from each other. A part of the plurality of patterns are scanned with an electron beam to charge the plurality of patterns. An intensity of secondary electrons emitted from the scanned part of the plurality of patterns is obtained. One or more of the plurality of patterns that show an intensity of the secondary electrons different from others of the plurality of patterns are searched.

Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

Abstract: A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.

Abstract: Systems and method for camera calibration. In one example, the camera includes an electronic processor configured to obtain a bounding box in a captured image, the bounding box bounding a person in the image and having a lowermost vertical coordinate and an uppermost vertical coordinate. The electronic processor determines an initial estimation of values of a set of camera parameters ? and a current estimation of values of the set of camera parameters ? based on the initial estimation. The electronic processor iteratively updates the current estimation of values of the set of camera parameters ? by determining feet coordinates within the bounding box, determining a vertical head coordinate, and updating the current estimation of values of the set of camera parameters ? by reducing a difference between the vertical head coordinate and the uppermost vertical coordinate of the bounding box.

Abstract: A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.

Abstract: A device monitors execution of a safety workflow, the safety workflow comprising one or more triggers and one or more responsive actions. The device provides, at a display screen, an indication of the safety workflow and respective visual indications of: a physical sensor that generated sensor data of a trigger of the safety workflow; and a communication device associated with a responsive action to the trigger. The device detects, via an input device, an interaction with one or more of the respective visual indications to interact with one or more of the physical sensor and the communication device. Based on the interaction, the device one or more of: initiates communication with the communication device; and sends the sensor data to the communication device.

Abstract: A light guide plate, a backlight module and a display device are provided. The light guide plate includes a main body and an optical layer. The main body has a light-incident surface, a side surface and an optical surface. The light-incident surface and the side surface are respectively connected to the optical surface. The optical layer is correspondingly disposed on the side surface of the main body. In a reflectance characteristic of the optical layer, a total reflectance of the reflectance characteristic is composed of the diffuse reflectance and the parallel reflectance. The percentage value of the parallel reflectance to the total reflectance is less than 45 and larger than 25, including the end point.

Abstract: A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.

Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

Abstract: A method for transferring a micro semiconductor element includes the following steps. A substrate, a bonding layer disposed on the substrate, and a supporting member disposed on the bonding layer opposite to the substrate are provided. The supporting member is bonded to a micro semiconductor element for supporting the same. A through hole is provided to extend through the substrate, the bonding layer, and the supporting member so as to forma transfer structure. A separation force is applied via the through hole to separate the micro semiconductor element from the supporting member.

Abstract: A device monitors execution of a safety workflow, the safety workflow comprising one or more triggers and one or more responsive actions. The device provides, at a display screen, an indication of the safety workflow and respective visual indications of: a physical sensor that generated sensor data of a trigger of the safety workflow; and a communication device associated with a responsive action to the trigger. The device detects, via an input device, an interaction with one or more of the respective visual indications to interact with one or more of the physical sensor and the communication device. Based on the interaction, the device one or more of: retrieves the sensor data; initiates communication with the communication device; and sends the sensor data to the communication device.

Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

Abstract: A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.

Abstract: Techniques for summarization of search results are provided. A similarity search query comprising at least one search criteria is received. The similarity search query is executed on at least one data source containing a plurality of images associated with metadata responsive to the search criteria. A plurality of search results response to the similarity search query is received from the at least one data source. The plurality of search results is clustered based on the metadata associated with the plurality of search results excluding the similarity criteria. The plurality of search results is summarized based on the results of the clustering. The summarization is displayed in a display view. An interactive user interface is provided to refine the plurality of search results based on the summarization.

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

Abstract: A memory device includes a plurality of word lines (WLs) above a substrate; a plurality of memory strings laterally isolated from each other, each of the plurality of memory strings being operatively coupled to a respective subset of the plurality of WLs; and a plurality of drivers, each of the plurality of drivers being configured to control a corresponding one of the plurality of WLs and including a first transistor having a first conductive type and a second transistor having a second conductive type opposite to the first conductive type.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: A micro light-emitting device includes a support structure with a cavity and at least one micro light-emitting element that includes a semiconductor structure accommodated by the cavity, at least one bridge connection member disposed on the semiconductor structure to interconnect the semiconductor structure and the support structure, and a protruding contact member disposed on at least one of the semiconductor structure and the bridge connection member and protruding therefrom to be configured to contact with a transfer means. The device is configured to contact with the transfer means at the protruding contact member of the element. A transfer method using the device is also disclosed.

Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

Abstract: Techniques for summarization of search results are provided. A similarity search query comprising at least one search criteria is received. The similarity search query is executed on at least one data source containing a plurality of images associated with metadata responsive to the search criteria. A plurality of search results response to the similarity search query is received from the at least one data source. The plurality of search results is clustered based on the metadata associated with the plurality of search results excluding the similarity criteria. The plurality of search results is summarized based on the results of the clustering. The summarization is displayed in a display view. An interactive user interface is provided to refine the plurality of search results based on the summarization.