Patents by Inventor Chia Ying Lee

Chia Ying Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200365249
    Abstract: A method for predicting immunotherapy response of a subject having cancer includes the following steps. A peripheral blood sample is obtained from the subject having cancer before or after receiving the immunotherapy. The number of immune cells in the peripheral blood sample of the subject having cancer is detected. The number of immune cells and a first cut-off value/or a second cut-off value are compared to indicate whether the subject having cancer benefits from the immunotherapy. The first cut-off value/or the second cut-off value is determined by the following steps: a statistical analysis of a correlation between the number of immune cells in a group of subjects having cancer and an expected risk of disease progression in the group of subjects having cancer is performed, and then a statistically significant value used to define the correlation is obtained.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 19, 2020
    Applicant: MiCareo Taiwan Co., Ltd.
    Inventors: Chia-Ying Lee, Ju-Yu Tseng, Hong-Ling Wang, Shin-Hang Wang, Jui-Lin Chen
  • Publication number: 20200345724
    Abstract: The present invention is directed to a depot composition for sustained release delivery of buprenorphine with enhanced stability and bioavailability. The composition is an injectable, low viscosity liquid and can form a depot in situ capable of delivering therapeutic level of buprenorphine over a period of time from one week to 3 months.
    Type: Application
    Filed: January 22, 2018
    Publication date: November 5, 2020
    Applicant: Foresee Pharmaceuticals Co., Ltd.
    Inventors: Yuhua LI, MingHsin LI, Chen-Chang LEE, Chia-Ying YANG, Chih-Ying LIN
  • Publication number: 20200335383
    Abstract: A micro device transferring apparatus includes a first conveying mechanism, a carrier unit, a push device and a release device. The first conveying mechanism includes a release tape having a release adhesive, a first roller connected to an end of the release tape, and a conveying device connected to a horizontal section of the release tape to drive the release tape to move in a moving direction. The carrier unit includes a first carrier holding multiple micro devices, and a second carrier for receiving the micro devices. The push device is for pushing the release tape to pick up the micro devices with the release adhesive. The release device is for decomposing the release adhesive to release the micro devices.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 22, 2020
    Inventors: CHEN-KE HSU, ZHIBAI ZHONG, CHIA-EN LEE, JINJIAN ZHENG, ZHENG WU, SHAO-YING TING
  • Publication number: 20200327867
    Abstract: The present disclosure discloses a head mounted display system including a tracking unit, a display unit and a processing unit coupled to the tracking unit and the display unit. The tracking unit is for tracking at least one of a position, an orientation and a pose of the head mounted display system and further generating a tracking result. The display unit is for displaying a virtual scene and a map of the real environment based on the tracking result in a picture-in-picture mode. The present disclosure allows a user to see the virtual scene and the map of the real environment in the picture-in-picture mode synchronously and help the user to understand a current position or a current state of the user in the real environment, which effectively ensures the user's safety and prevents injuries caused by collision when the user experiences the virtual environment.
    Type: Application
    Filed: April 15, 2019
    Publication date: October 15, 2020
    Inventors: Tzu-Chiang Wang, Chia-Chun Lee, Si-Ying Li, Wei-Shuo Chen
  • Publication number: 20200321294
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first bonding layer formed below a first substrate, a first bonding via formed through the first oxide layer and the first bonding layer, a first dummy pad formed in the first bonding layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over a second substrate, a second bonding via formed through the second bonding layer, and a second dummy pad formed in the second bonding layer. The semiconductor structure includes a bonding structure between the first substrate and the second substrate, wherein the bonding structure includes the first bonding via bonded to the second bonding via and the first dummy pad bonded to the second dummy pad.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu WEI, Cheng-Yuan LI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
  • Publication number: 20200321392
    Abstract: Disclosed is a micro light-emitting component, a micro light-emitting diode, and a transfer layer. The transfer layer has a recess for receiving the micro light-emitting diode to permit the micro light-emitting diode to be retained by the transfer layer, and is transformable from a first state, in which the transfer layer is deformed by the micro light-emitting diode to form the recess, to a second state, in which the micro light-emitting diode received in the recess is retained by the transfer layer. Also disclosed are micro light-emitting component matrix and a method for manufacturing the micro light-emitting component matrix.
    Type: Application
    Filed: June 19, 2020
    Publication date: October 8, 2020
    Applicant: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.
    Inventors: Shao-Ying TING, Junfeng FAN, Chia-En LEE, Chen-Ke HSU
  • Patent number: 10797174
    Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Tai Chang, Tung Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
  • Patent number: 10790321
    Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a floating diffusion region disposed at one side of a transfer gate within a substrate and a photo detecting column disposed at the other side of the transfer gate opposing to the floating diffusion region within the substrate. The photo detecting column comprises a doped sensing layer with a doping type opposite to that of the substrate. The photo detecting column and the substrate are in contact with each other at a junction interface comprising one or more recessed portions. By forming the junction interface with recessed portions, the junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wei, Hsin-Chi Chen, Kuo-Cheng Lee, Ping-Hao Lin, Hsun-Ying Huang, Yen-Liang Lin, Yu Ting Kao
  • Publication number: 20200286738
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Inventors: RU-GUN LIU, CHENG-HSIUNG TSAI, CHUNG-JU LEE, CHIH-MING LAI, CHIA-YING LEE, JYU-HORNG SHIEH, KEN-HSIEN HSIEH, MING-FENG SHIEH, SHAU-LIN SHUE, SHIH-MING CHANG, TIEN-I BAO, TSAI-SHENG GAU
  • Publication number: 20200273996
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
  • Publication number: 20200273997
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
  • Publication number: 20200248612
    Abstract: A plural-fans driving apparatus is provided to drive a first fan and a second fan, and the first fan and the second fan are three-phase fans. The plural-fans driving apparatus includes a controller, a first three-phase motor driver structure, a second three-phase motor driver structure, and a protection and input interface circuit. The protection and input interface circuit is coupled to the first three-phase motor driver structure and the second three-phase motor driver structure, and protects the first three-phase motor driver structure and the second three-phase motor driver structure. The controller controls the first three-phase motor driver structure to drive the first fan, and controls the second three-phase motor driver structure to drive the second fan.
    Type: Application
    Filed: April 23, 2020
    Publication date: August 6, 2020
    Inventors: Kuo-Ying LEE, Feng-Ying LIN, Meng-Yu CHEN, Chia-Ching TSAI
  • Publication number: 20200234972
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a first hard mask layer over a substrate and forming a second hard mask layer over the first hard mask layer. The second hard mask layer is patterned to define an island having a first width along a first direction. The island is patterned to form a patterned island having a second width along the first direction that is less than the first width. A sacrificial mask is formed over the first hard mask layer and the first hard mask layer is patterned according to the patterned island and the sacrificial mask.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 23, 2020
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 10720708
    Abstract: An antenna device includes a first dielectric substrate, a first radiator disposed on the first dielectric substrate, a second dielectric substrate disposed on the first radiator, a second radiator disposed between the first dielectric substrate and the second dielectric substrate, a main radiator, disposed on the second dielectric substrate, and a modulation structure located between a first radiation portion of the first radiator and a second radiation portion of the second radiator. The first radiation portion, the modulation structure, and the second radiation portion are located in a central area.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: July 21, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Huei-Ying Chen, I-Yin Li, Chia-Chi Ho, Hsu-Kuan Hsu, Ker-Yih Kao, Chung-Kuang Wei, Chin-Lung Ting, Cheng-Chi Wang, Chien-Hsing Lee
  • Publication number: 20200227302
    Abstract: A method for transferring a micro semiconductor element includes the following steps. A substrate, a bonding layer disposed on the substrate, and a supporting member disposed on the bonding layer opposite to the substrate are provided. The supporting member is bonded to a micro semiconductor element for supporting the same. A through hole is provided to extend through the substrate, the bonding layer, and the supporting member so as to forma transfer structure. A separation force is applied via the through hole to separate the micro semiconductor element from the supporting member.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Inventors: ZHENG WU, SHAO-YING TING, CHIA-EN LEE, CHEN-KE HSU
  • Patent number: 10707347
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Yuan, Chia-Cheng Ho, Tzu-Chung Wang, Tung Ying Lee, Jin Cai, Ming-Shiang Lin
  • Publication number: 20200212244
    Abstract: A photodetector includes: a substrate; a first semiconductor region, the first semiconductor region extending into the substrate from a front side of the substrate; and a second semiconductor region, the second semiconductor region further extending into the substrate from a bottom boundary of the first semiconductor region, wherein when the photodetector operates under a Geiger mode, the second semiconductor region is fully depleted to absorb a radiation source received from a back side of the substrate.
    Type: Application
    Filed: March 13, 2020
    Publication date: July 2, 2020
    Inventors: Chia-Yu WEI, Yu-Ting KAO, Yen-Liang LIN, Wen-I HSU, Hsun-Ying HUANG, Kuo-Cheng LEE, Hsin-Chi CHEN
  • Patent number: 10692826
    Abstract: A semiconductor structure is provided. A first semiconductor device includes a first conductive layer formed over a first substrate; a first etching stop layer formed over the first conductive layer, and the first etching stop layer is in direct contact with the first conductive layer. A first bonding layer is formed over the first etching stop layer, and a first bonding via is formed through the first bonding layer and the first etching stop layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over the second etching stop layer and a second bonding via formed through the second bonding layer and a second etching stop layer. A bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Patent number: D895063
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: September 1, 2020
    Assignee: KOHLER CO.
    Inventors: Han Chew, Sophie Su, Chia Ying Lee
  • Patent number: D903052
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: November 24, 2020
    Assignee: BEIJING KOHLER LTD.
    Inventors: Han Chew, Sophie Su, Chia Ying Lee