Patents by Inventor Chia Ying Lee

Chia Ying Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10707347
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Yuan, Chia-Cheng Ho, Tzu-Chung Wang, Tung Ying Lee, Jin Cai, Ming-Shiang Lin
  • Publication number: 20200212244
    Abstract: A photodetector includes: a substrate; a first semiconductor region, the first semiconductor region extending into the substrate from a front side of the substrate; and a second semiconductor region, the second semiconductor region further extending into the substrate from a bottom boundary of the first semiconductor region, wherein when the photodetector operates under a Geiger mode, the second semiconductor region is fully depleted to absorb a radiation source received from a back side of the substrate.
    Type: Application
    Filed: March 13, 2020
    Publication date: July 2, 2020
    Inventors: Chia-Yu WEI, Yu-Ting KAO, Yen-Liang LIN, Wen-I HSU, Hsun-Ying HUANG, Kuo-Cheng LEE, Hsin-Chi CHEN
  • Patent number: 10692826
    Abstract: A semiconductor structure is provided. A first semiconductor device includes a first conductive layer formed over a first substrate; a first etching stop layer formed over the first conductive layer, and the first etching stop layer is in direct contact with the first conductive layer. A first bonding layer is formed over the first etching stop layer, and a first bonding via is formed through the first bonding layer and the first etching stop layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over the second etching stop layer and a second bonding via formed through the second bonding layer and a second etching stop layer. A bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Publication number: 20200188465
    Abstract: The present invention provides a new method for decreasing level of a proinflammatory cytokine in a subject, which is further able to treating cytokine release syndrome caused by CAR T-cell therapy or a disorder mediated by an overproduction of a proinflammatory cytokine. The method comprises administering to the subject in need thereof a therapeutically effective amount of a pharmaceutical composition which is comprising at least one selected from the group consisting of Phenothiazine derivatives, Graptopetalum paraguayense extract, Rhodiola rosea extract and Histone Deacetylase (HDAC) inhibitors.
    Type: Application
    Filed: December 11, 2019
    Publication date: June 18, 2020
    Inventors: Yu-Chen Tsai, Chi-Ying Huang, Ming-Hsi Chuang, Po-Cheng Lin, Chia-Hsin Lee
  • Publication number: 20200193676
    Abstract: Methods and apparatus of processing 360-degree virtual reality images are disclosed. According to one method, the method receives coded data for an extended 2D (two-dimensional) frame including an encoded 2D frame with one or more encoded guard bands, wherein the encoded 2D frame is projected from a 3D (three-dimensional) sphere using a target projection, wherein said one or more encoded guard bands are based on a blending of one or more guard bands with an overlapped region when the overlapped region exists. The method then decodes the coded data into a decoded extended 2D frame including a decoded 2D frame with one or more decoded guard bands, and derives a reconstructed 2D frame from the decoded extended 2D frame.
    Type: Application
    Filed: February 27, 2020
    Publication date: June 18, 2020
    Inventors: Cheng-Hsuan SHIH, Chia-Ying LI, Ya-Hsuan LEE, Hung-Chih LIN, Jian-Liang LIN, Shen-Kai CHANG
  • Publication number: 20200185440
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 11, 2020
    Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
  • Patent number: 10665467
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee, Jyu-Horng Shieh, Ken-Hsien Hsieh, Ming-Feng Shieh, Shau-Lin Shue, Shih-Ming Chang, Tien-I Bao, Tsai-Sheng Gau
  • Patent number: 10651047
    Abstract: In some embodiments, the disclosure relates to an integrated circuit structure. The integrated circuit structure has a substrate and a first hard mask layer over the substrate. An island of a second hard mask layer is arranged on the first hard mask layer and is set back from sidewalls of the first hard mask layer. A sacrificial mask is disposed over the island of the second hard mask layer. The sacrificial mask has sidewalls that define an opening exposing upper surfaces of the first hard mask layer and the island of the second hard mask layer. The island of the second hard mask layer extends from below the sacrificial mask to laterally past the sidewalls of the sacrificial mask.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 10637015
    Abstract: The disclosure provides seals for devices that operate at elevated temperatures and have reactive metal vapors, such as lithium, sodium or magnesium. In some examples, such devices include energy storage devices that may be used within an electrical power grid or as part of a standalone system. The energy storage devices may be charged from an electricity production source for later discharge, such as when there is a demand for electrical energy consumption.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: April 28, 2020
    Assignee: AMBRI INC.
    Inventors: Greg Thompson, David J. Bradwell, Vimal Pujari, Chia-Ying Lee, David McCleary, Jennifer Cocking, James D. Fritz
  • Publication number: 20200127138
    Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
    Type: Application
    Filed: January 23, 2019
    Publication date: April 23, 2020
    Inventors: Feng Yuan, Chia-Cheng Ho, Tzu-Chung Wang, Tung Ying Lee, Jin Cai, Ming-Shiang Lin
  • Patent number: 10629765
    Abstract: A photodetector includes: a substrate having a first doping type; a first semiconductor region having a second doping type, the first semiconductor region extending into the substrate from a front side of the substrate; and a second semiconductor region having the first doping type, the second semiconductor region further extending into the substrate from a bottom boundary of the first semiconductor region, wherein when the photodetector operates under a Geiger mode, the second semiconductor region is fully depleted to absorb a radiation source received from a back side of the substrate.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wei, Yu-Ting Kao, Yen-Liang Lin, Wen-I Hsu, Hsun-Ying Huang, Kuo-Cheng Lee, Hsin-Chi Chen
  • Publication number: 20200111670
    Abstract: The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material over an underlying layer. The spacer material has sidewalls defining a first trench. A cut material is formed over the spacer material and within the first trench. The cut material separates the trench into a pair of trench segments having ends separated by the cut material. The underlying layer is patterned according to the spacer material and the cut material.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 9, 2020
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Patent number: 10614609
    Abstract: Methods and apparatus of processing 360-degree virtual reality images are disclosed. According to one method, a 2D (two-dimensional) frame is divided into multiple blocks. The multiple blocks are encoded or decoded using quantization parameters by restricting a delta quantization parameter to be within a threshold for any two blocks corresponding to two neighboring blocks on a 3D sphere. According to another embodiment, one or more guard bands are added to one or more edges that are discontinuous in the 2D frame but continuous in the 3D sphere. Fade-out process is applied to said one or more guard bands to generate one or more faded guard bands. At the decoder side, the reconstructed 2D frame is generated from the decoded extended 2D frame by cropping said one or more decoded faded guard bands or by blending said one or more decoded faded guard bands and reconstructed duplicated areas.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: April 7, 2020
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Hsuan Shih, Chia-Ying Li, Ya-Hsuan Lee, Hung-Chih Lin, Jian-Liang Lin, Shen-Kai Chang
  • Publication number: 20200097769
    Abstract: Methods, systems, and techniques for object detection and tracking are provided. A system may include a module configured to generate a plurality of region proposals, each region proposal comprising a part of a video frame, a CNN pre-trained for object detection, the plurality of region proposals being input to the CNN; a tracker for tracking one or more targets based on outputs from the CNN across the series of video frames and generating tracking information on the one or more targets; and a module further configured to refine the plurality of region proposals to be input to the CNN, based on the tracking information.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 26, 2020
    Applicant: Avigilon Corporation
    Inventors: Aleksey Lipchin, Yin Wang, Xiao Xiao, Hao Zhang, Chia Ying Lee
  • Publication number: 20200083110
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 10573076
    Abstract: A video processing method includes: receiving an omnidirectional image/video content corresponding to a viewing sphere, generating a sequence of projection-based frames according to the omnidirectional image/video content and a viewport-based cube projection layout, and encoding the sequence of projection-based frames to generate a bitstream. Each projection-based frame has a 360-degree image/video content represented by rectangular projection faces packed in the viewport-based cube projection layout. The rectangular projection faces include a first rectangular projection face, a second rectangular projection face, a third rectangular projection face, a fourth rectangular projection face, a fifth rectangular projection face, and a sixth rectangular projection face split into partial rectangular projection faces.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: February 25, 2020
    Assignee: MEDIATEK INC.
    Inventors: Hung-Chih Lin, Chia-Ying Li, Le Shi, Ya-Hsuan Lee, Jian-Liang Lin, Shen-Kai Chang
  • Publication number: 20200058784
    Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.
    Type: Application
    Filed: August 17, 2018
    Publication date: February 20, 2020
    Inventors: Kai-Tai CHANG, Tung Ying LEE, Wei-Sheng YUN, Tzu-Chung WANG, Chia-Cheng HO, Ming-Shiang LIN, Tzu-Chiang CHEN
  • Publication number: 20200058689
    Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a floating diffusion region disposed at one side of a transfer gate within a substrate and a photo detecting column disposed at the other side of the transfer gate opposing to the floating diffusion region within the substrate. The photo detecting column comprises a doped sensing layer with a doping type opposite to that of the substrate. The photo detecting column and the substrate are in contact with each other at a junction interface comprising one or more recessed portions. By forming the junction interface with recessed portions, the junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Inventors: Chia-Yu Wei, Hsin-Chi Chen, Kuo-Cheng Lee, Ping-Hao Lin, Hsun-Ying Huang, Yen-Liang Lin, Yu Ting Kao
  • Publication number: 20200058763
    Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.
    Type: Application
    Filed: September 5, 2019
    Publication date: February 20, 2020
    Inventors: Kai-Tai CHANG, Tung Ying LEE, Wei-Sheng YUN, Tzu-Chung WANG, Chia-Cheng HO, Ming-Shiang LIN, Tzu-Chiang CHEN
  • Patent number: 10566361
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: February 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yu Wei, Fu-Cheng Chang, Hsin-Chi Chen, Ching-Hung Kao, Chia-Pin Cheng, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin