Patents by Inventor Chia Ying Lee

Chia Ying Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cut first self-aligned litho-etch patterning
    Patent number: 10109486
    Abstract: The present disclosure relates to an integrated chip formed by a self-aligned litho-etch process. In some embodiments, the integrated chip has a first plurality of shapes of an integrated chip layer arranged along a first direction at a first pitch. The first plurality of shapes include a first two shapes separated by a first end-to-end space along a second direction perpendicular to the first direction. A second plurality of shapes of the integrated chip layer are arranged along the first direction at a second pitch. The second plurality of shapes include a second two shapes separated by a second end-to-end space along the second direction. A ratio of the first end-to-end space to the second end-to-end space is approximately equal to 2.5:1.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Double patterning method
    Patent number: 10109497
    Abstract: In some embodiments, the disclosure relates to a method of forming an integrated circuit. The method is performed by forming a first mask layer over a substrate and a second mask layer over the first mask layer. The second mask layer is patterned to form cut regions that include a part of the second mask layer remaining after patterning. A mandrel is formed directly over the first mask layer after patterning the second mask layer. The first mask layer is etched according to a sacrificial mask formed using the mandrel and according to the cut regions to form a patterned first mask. The cut regions extend from within the sacrificial mask to laterally past sidewalls of the sacrificial mask. The substrate is processed according to the patterned first mask.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • METHODS FOR DIAGNOSING AND TREATING CANCER
    Publication number: 20180267046
    Abstract: Disclosed is a method for identifying a subject at risk of developing a recurrent or metastatic cancer, comprising detecting PD-L1+ circulating tumor cells in a blood sample, a tissue fluid sample or a specimen of the subject. Also disclosed is method for treating a cancer comprising identifying a subject having one ore more PD-L1+ circulating tumor cells by detecting PD-L1+ circulating tumor cells in a blood sample, a tissue fluid sample or a specimen of the subject, and administering a treatment to the subject.
    Type: Application
    Filed: March 13, 2018
    Publication date: September 20, 2018
    Applicant: MiCareo Taiwan Co., Ltd.
    Inventors: Ju-Yu Tseng, Yen-Ru Chen, Chia-Ying Lee, Li-Fan Wu, Shin-Hang Wang, Jui-Lin Chen, Chwen-Cheng Chen
  • VOLTAGE-ENHANCED ENERGY STORAGE DEVICES
    Publication number: 20180159179
    Abstract: The present disclosure provides an energy storage device comprising at least one electrochemical cell comprising a negative current collector, a negative electrode in electrical communication with the negative current collector, an electrolyte in electrical communication with the negative electrode, a positive electrode in electrical communication with the electrolyte and a positive current collector in electrical communication with the positive electrode. The negative electrode comprises an alkali metal. Upon discharge, the electrolyte provides charged species of the alkali metal. The positive electrode can include a Group IIIA, IVA, VA and VIA of the periodic table of the elements, or a transition metal (e.g., Group 12 element).
    Type: Application
    Filed: December 8, 2017
    Publication date: June 7, 2018
    Inventors: David J. Bradwell, Xingwen Yu, Greg A. Thompson, Jianyi Cui, Alex Elliott, Chia-Ying Lee, Denis Tite
  • CERAMIC MATERIALS AND SEALS FOR HIGH TEMPERATURE REACTIVE MATERIAL DEVICES
    Publication number: 20180090726
    Abstract: The disclosure provides seals for devices that operate at elevated temperatures and have reactive metal vapors, such as lithium, sodium or magnesium. In some examples, such devices include energy storage devices that may be used within an electrical power grid or as part of a standalone system. The energy storage devices may be charged from an electricity production source for later discharge, such as when there is a demand for electrical energy consumption.
    Type: Application
    Filed: August 30, 2017
    Publication date: March 29, 2018
    Inventors: Greg Thompson, David J. Bradwell, Vimal Pujari, Chia-Ying Lee, David McCleary, Jennifer Cocking, James D. Fritz
  • Nano wire structure and method for fabricating the same
    Patent number: 9911661
    Abstract: A method includes depositing a sacrificial layer on a first dielectric layer over a substrate; applying a first patterning process, a second patterning process, a third patterning process to the sacrificial layer to form a first group of openings, a second group of openings and a third group of openings, respectively, in the sacrificial layer, wherein three first openings from three different patterning processes form a first side, a second side and a first angle between the first side and the second side, and three second openings from the three different patterning processes form a third side, a fourth side and a second angle between the third side and the fourth side, wherein the first angle is approximately equal to the second angle and forming nanowires based on the first group of openings, the second group of openings and the third group of openings.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Voltage-enhanced energy storage devices
    Patent number: 9876258
    Abstract: The present disclosure provides an energy storage device comprising at least one electrochemical cell comprising a negative current collector, a negative electrode in electrical communication with the negative current collector, an electrolyte in electrical communication with the negative electrode, a positive electrode in electrical communication with the electrolyte and a positive current collector in electrical communication with the positive electrode. The negative electrode comprises an alkali metal. Upon discharge, the electrolyte provides charged species of the alkali metal. The positive electrode can include a Group IIIA, IVA, VA and VIA of the periodic table of the elements, or a transition metal (e.g., Group 12 element).
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: January 23, 2018
    Assignee: AMBRI INC.
    Inventors: David J. Bradwell, Xingwen Yu, Greg A. Thompson, Jianyi Cui, Alex Elliott, Chia-Ying Lee, Denis Tite
  • Method of fine line space resolution lithography for integrated circuit features using double patterning technology
    Patent number: 9865500
    Abstract: A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • CUT LAST SELF-ALIGNED LITHO-ETCH PATTERNING
    Publication number: 20170365472
    Abstract: The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material having vertically extending segments along sidewalls of a masking layer and a horizontally extending segment connecting the vertically extending segments. A cut material is formed over a part of the horizontally extending segment, and the horizontally extending segment of the spacer material not covered by the cut material is removed. A layer under the masking layer is patterned according to the masking layer and the spacer material.
    Type: Application
    Filed: September 6, 2017
    Publication date: December 21, 2017
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Nano Wire Structure and Method for Fabricating the Same
    Publication number: 20170365524
    Abstract: A method includes depositing a sacrificial layer on a first dielectric layer over a substrate; applying a first patterning process, a second patterning process, a third patterning process to the sacrificial layer to form a first group of openings, a second group of openings and a third group of openings, respectively, in the sacrificial layer, wherein three first openings from three different patterning processes form a first side, a second side and a first angle between the first side and the second side, and three second openings from the three different patterning processes form a third side, a fourth side and a second angle between the third side and the fourth side, wherein the first angle is approximately equal to the second angle and forming nanowires based on the first group of openings, the second group of openings and the third group of openings.
    Type: Application
    Filed: August 18, 2017
    Publication date: December 21, 2017
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Reverse tone self-aligned contact
    Patent number: 9812536
    Abstract: The present disclosure relate to a method to an integrated chip having a source/drain self-aligned contact to a transistor or other semiconductor device. In some embodiments, the integrated chip has a pair of gate structures including a gate electrode arranged over a substrate and an insulating material arranged over the gate electrode. A source/drain region is arranged within the substrate between the pair of gate structures. An etch stop layer is arranged along sidewalls of the pair of gate structures and over the source/drain region, and a dielectric layer is over the insulating material. A source/drain contact is arranged over the insulating material and the etch stop layer and is separated from the sidewalls of the pair of gate structures by the etch stop layer. The source/drain contact is electrically coupled to the source/drain region.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Feng Fu, Yu-Chan Yen, Chia-Ying Lee
  • Double Patterning Method
    Publication number: 20170309495
    Abstract: In some embodiments, the disclosure relates to a method of forming an integrated circuit. The method is performed by forming a first mask layer over a substrate and a second mask layer over the first mask layer. The second mask layer is patterned to form cut regions that include a part of the second mask layer remaining after patterning. A mandrel is formed directly over the first mask layer after patterning the second mask layer. The first mask layer is etched according to a sacrificial mask formed using the mandrel and according to the cut regions to form a patterned first mask. The cut regions extend from within the sacrificial mask to laterally past sidewalls of the sacrificial mask. The substrate is processed according to the patterned first mask.
    Type: Application
    Filed: July 13, 2017
    Publication date: October 26, 2017
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • CUT FIRST SELF-ALIGNED LITHO-ETCH PATTERNING
    Publication number: 20170294311
    Abstract: The present disclosure relates to an integrated chip formed by a self-aligned litho-etch process. In some embodiments, the integrated chip has a first plurality of shapes of an integrated chip layer arranged along a first direction at a first pitch. The first plurality of shapes include a first two shapes separated by a first end-to-end space along a second direction perpendicular to the first direction. A second plurality of shapes of the integrated chip layer are arranged along the first direction at a second pitch. The second plurality of shapes include a second two shapes separated by a second end-to-end space along the second direction. A ratio of the first end-to-end space to the second end-to-end space is approximately equal to 2.5:1.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 12, 2017
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Cut last self-aligned litho-etch patterning
    Patent number: 9761451
    Abstract: The present disclosure relates to a method of performing a semiconductor fabrication process. In some embodiments, the method is performed by forming a spacer material within openings in a first masking layer overlying a second masking layer, and forming a reverse material over a part of the spacer material. A first plurality of openings are formed within the spacer material. The first plurality of openings are separated by the reverse material. A second plurality of openings are formed within the first masking layer. The second plurality of openings are separated by the spacer material. The second masking layer is patterned according to the first plurality of openings and the second plurality of openings.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: September 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Nano wire structure and method for fabricating the same
    Patent number: 9741621
    Abstract: A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Self-Aligned Nanowire Formation Using Double Patterning
    Publication number: 20170229349
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • VOLTAGE-ENHANCED ENERGY STORAGE DEVICES
    Publication number: 20170222273
    Abstract: The present disclosure provides an energy storage device comprising at least one electrochemical cell comprising a negative current collector, a negative electrode in electrical communication with the negative current collector, an electrolyte in electrical communication with the negative electrode, a positive electrode in electrical communication with the electrolyte and a positive current collector in electrical communication with the positive electrode. The negative electrode comprises an alkali metal. Upon discharge, the electrolyte provides charged species of the alkali metal. The positive electrode can include a Group IIIA, IVA, VA and VIA of the periodic table of the elements, or a transition metal (e.g., Group 12 element).
    Type: Application
    Filed: October 10, 2016
    Publication date: August 3, 2017
    Inventors: David J. Bradwell, Xingwen Yu, Greg A. Thompson, Jianyi Cui, Alex Elliott, Chia-Ying Lee, Denis Tite
  • Faucet
    Patent number: D803988
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: November 28, 2017
    Assignee: KOHLER (CHINA) INVESTMENT CO., LTD.
    Inventors: Jimin Niu, Chia Ying Lee, Lun Cheak Tan
  • Faucet
    Patent number: D821547
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: June 26, 2018
    Assignee: KOHLER (CHINA) INVESTMENT CO., LTD.
    Inventors: Jimin Niu, Chia Ying Lee, Lun Cheak Tan
  • Hand shower
    Patent number: D828906
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: September 18, 2018
    Assignee: KOHLER CHINA INVESTMENT CO. LTD.
    Inventors: Tsung-Yu Lu, Chia-Ying Lee, Lun Cheak Tan