Patents by Inventor Chia Ying Lee

Chia Ying Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9865500
    Abstract: A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Publication number: 20170365524
    Abstract: A method includes depositing a sacrificial layer on a first dielectric layer over a substrate; applying a first patterning process, a second patterning process, a third patterning process to the sacrificial layer to form a first group of openings, a second group of openings and a third group of openings, respectively, in the sacrificial layer, wherein three first openings from three different patterning processes form a first side, a second side and a first angle between the first side and the second side, and three second openings from the three different patterning processes form a third side, a fourth side and a second angle between the third side and the fourth side, wherein the first angle is approximately equal to the second angle and forming nanowires based on the first group of openings, the second group of openings and the third group of openings.
    Type: Application
    Filed: August 18, 2017
    Publication date: December 21, 2017
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Publication number: 20170365472
    Abstract: The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material having vertically extending segments along sidewalls of a masking layer and a horizontally extending segment connecting the vertically extending segments. A cut material is formed over a part of the horizontally extending segment, and the horizontally extending segment of the spacer material not covered by the cut material is removed. A layer under the masking layer is patterned according to the masking layer and the spacer material.
    Type: Application
    Filed: September 6, 2017
    Publication date: December 21, 2017
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Patent number: 9812536
    Abstract: The present disclosure relate to a method to an integrated chip having a source/drain self-aligned contact to a transistor or other semiconductor device. In some embodiments, the integrated chip has a pair of gate structures including a gate electrode arranged over a substrate and an insulating material arranged over the gate electrode. A source/drain region is arranged within the substrate between the pair of gate structures. An etch stop layer is arranged along sidewalls of the pair of gate structures and over the source/drain region, and a dielectric layer is over the insulating material. A source/drain contact is arranged over the insulating material and the etch stop layer and is separated from the sidewalls of the pair of gate structures by the etch stop layer. The source/drain contact is electrically coupled to the source/drain region.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Feng Fu, Yu-Chan Yen, Chia-Ying Lee
  • Publication number: 20170309495
    Abstract: In some embodiments, the disclosure relates to a method of forming an integrated circuit. The method is performed by forming a first mask layer over a substrate and a second mask layer over the first mask layer. The second mask layer is patterned to form cut regions that include a part of the second mask layer remaining after patterning. A mandrel is formed directly over the first mask layer after patterning the second mask layer. The first mask layer is etched according to a sacrificial mask formed using the mandrel and according to the cut regions to form a patterned first mask. The cut regions extend from within the sacrificial mask to laterally past sidewalls of the sacrificial mask. The substrate is processed according to the patterned first mask.
    Type: Application
    Filed: July 13, 2017
    Publication date: October 26, 2017
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Publication number: 20170294311
    Abstract: The present disclosure relates to an integrated chip formed by a self-aligned litho-etch process. In some embodiments, the integrated chip has a first plurality of shapes of an integrated chip layer arranged along a first direction at a first pitch. The first plurality of shapes include a first two shapes separated by a first end-to-end space along a second direction perpendicular to the first direction. A second plurality of shapes of the integrated chip layer are arranged along the first direction at a second pitch. The second plurality of shapes include a second two shapes separated by a second end-to-end space along the second direction. A ratio of the first end-to-end space to the second end-to-end space is approximately equal to 2.5:1.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 12, 2017
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Patent number: 9761451
    Abstract: The present disclosure relates to a method of performing a semiconductor fabrication process. In some embodiments, the method is performed by forming a spacer material within openings in a first masking layer overlying a second masking layer, and forming a reverse material over a part of the spacer material. A first plurality of openings are formed within the spacer material. The first plurality of openings are separated by the reverse material. A second plurality of openings are formed within the first masking layer. The second plurality of openings are separated by the spacer material. The second masking layer is patterned according to the first plurality of openings and the second plurality of openings.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: September 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Patent number: 9741621
    Abstract: A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Publication number: 20170229349
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Publication number: 20170222273
    Abstract: The present disclosure provides an energy storage device comprising at least one electrochemical cell comprising a negative current collector, a negative electrode in electrical communication with the negative current collector, an electrolyte in electrical communication with the negative electrode, a positive electrode in electrical communication with the electrolyte and a positive current collector in electrical communication with the positive electrode. The negative electrode comprises an alkali metal. Upon discharge, the electrolyte provides charged species of the alkali metal. The positive electrode can include a Group IIIA, IVA, VA and VIA of the periodic table of the elements, or a transition metal (e.g., Group 12 element).
    Type: Application
    Filed: October 10, 2016
    Publication date: August 3, 2017
    Inventors: David J. Bradwell, Xingwen Yu, Greg A. Thompson, Jianyi Cui, Alex Elliott, Chia-Ying Lee, Denis Tite
  • Patent number: 9711372
    Abstract: In some embodiments, the disclosure relates to a method of forming an integrated circuit device. The method is performed by forming a first mask layer over a substrate and a second mask layer over the first mask layer. The second mask layer is patterned to form cut regions. A mandrel is formed over the first mask layer and the cut regions, and the first mask layer is etched using the mandrel form a patterned first mask. The substrate is etched according to the patterned first mask and the cut regions to form trenches in the substrate, and the trenches are filled with conductive metal to form conductive lines.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Publication number: 20170194198
    Abstract: A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.
    Type: Application
    Filed: March 21, 2017
    Publication date: July 6, 2017
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 9698016
    Abstract: The present disclosure relates to a method for performing a self-aligned litho-etch (SALE) process. In some embodiments, the method is performed by forming a first cut layer over a hard mask having a first layer and an underlying second layer. A first plurality of openings are formed within the first layer and expose the second layer at a first plurality of positions. Two or more of the first plurality of openings are separated by the first cut layer. A spacer material is selectively formed onto sidewalls of the first plurality of openings within the first layer. A second plurality of openings are then formed within the first layer. The second plurality of openings are separated by a second cut layer including the spacer material and expose the second layer at a second plurality of positions. The second layer is etched according to the first layer and the spacer material.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Publication number: 20170154824
    Abstract: A method comprises depositing a sacrificial layer on a first dielectric layer over a substrate, applying a first patterning process, a second patterning process, a third patterning process and a fourth patterning process to the sacrificial layer to form a first group of openings, a second group of openings, a third group of openings and a fourth group of openings, respectively, in the sacrificial layer, wherein openings from different patterning processes are arranged in an alternating manner and four openings of the opening from the different patterning processes form a diamond shape and forming nanowires based on the first group of openings, the second group of openings, the third group of openings and the fourth group of openings.
    Type: Application
    Filed: February 10, 2017
    Publication date: June 1, 2017
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Publication number: 20170145001
    Abstract: The present disclosure provides processes for preparing brexpiprazole. The present disclosure also provides processes for the purification of brexpiprazole. The processes for preparing and purifying brexpiprazole of the present invention provide substantial improvements over currently known methods. In certain embodiments, the conversion of Formula XI and XII to form XIII provides increased selectivity over previously reported methods. This offers increased yield and purity. The improved process for purifying brexpiprazole disclosed herein provides brexpiprazole with superior purity and is also more suitable for industrial production.
    Type: Application
    Filed: November 1, 2016
    Publication date: May 25, 2017
    Inventors: Chia-Ying LEE, Shu Ting HUANG, Hsin-Chi WANG, Yuan-Xiu LIAO, Jiunn-Cheh GUO, Lung-Huang KUO
  • Patent number: 9633907
    Abstract: A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 9613903
    Abstract: A hard mask is disposed over a base material, and an I-shaped first opening is disposed in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 9601344
    Abstract: The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ying Lee, Chih-Yuan Ting, Jyu-Horng Shieh, Ming-Hsing Tsai, Syun-Ming Jang
  • Publication number: 20170069505
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 9, 2017
    Inventors: RU-GUN LIU, CHENG-HSIUNG TSAI, CHUNG-JU LEE, CHIH-MING LAI, CHIA-YING LEE, JYU-HORNG SHIEH, KEN-HSIEN HSIEH, MING-FENG SHIEH, SHAU-LIN SHUE, SHIH-MING CHANG, TIEN-I BAO, TSAI-SHENG GAU
  • Patent number: D803988
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: November 28, 2017
    Assignee: KOHLER (CHINA) INVESTMENT CO., LTD.
    Inventors: Jimin Niu, Chia Ying Lee, Lun Cheak Tan