Patents by Inventor Chiaki Takubo

Chiaki Takubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5615822
    Abstract: In this invention, a designed value of a lead width is previously input and a bonding load suitable for the designed lead width is previously input before the step of continuously bonding a TAB tape on a semiconductor chip is effected. Next, the TAB tape and chip are carried to preset positions, and after recognition of the positions of the tape and chip and the alignment of the tape and chip by use of a CCD camera are completed, the inner lead width is actually measured by use of the CCD camera. The measured lead width is compared with the designed lead width, and when a difference therebetween exceeds a preset reference value, the bonding load is changed to a bonding load suitable for the measured lead width of the lead to be actually bonded based on the ratio of the measured lead width to the designed lead width and then the bonding operation is effected by the suitable bonding load.
    Type: Grant
    Filed: September 22, 1995
    Date of Patent: April 1, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiaki Takubo, Hiroshi Tazawa, Eiichi Hosomi, Koji Shibasaki
  • Patent number: 5543663
    Abstract: A first thermal conductive member and a plurality of second thermal conductive members are formed on one major surface of an insulating board. A TCP is mounted on the first thermal conductive member. A heat sink is mounted on the plurality of second thermal conductive members. A third thermal conductive member is formed on the other major surface of the insulating board. A plurality of through holes are formed in the insulating board between the first and third thermal conductive members and between the second and third thermal conductive members. Fourth thermal conductive members are formed in the plurality of through holes. Heat generated by the semiconductor chip of the TCP is conducted to the heat sink through the first to fourth thermal conductive members. Therefore, a semiconductor device with excellent heat dissipation without damaging a semiconductor element can be provided.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: August 6, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Chiaki Takubo
  • Patent number: 5533664
    Abstract: In bonding the connecting electrodes of adjacent semiconductor chips to each other, a solder layer shaped like a bump is formed on that portion of the connecting electrode which is positioned on the upper surface of the semiconductor chip. The semiconductor chips are positioned close to each other such that the connecting electrodes of these chips are aligned with each other. Then, the solder layer is melted to cause the molten solder to flow along the entire region of the connecting electrode and, thus, to achieve mutual bonding of the connecting electrodes in the entire regions including the upper surface region and the side surface region. The method permits stably bonding semiconductor chips to each other with a high bonding strength, leading to an improved reliability of electric connection in the bonded portion.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: July 9, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mamoru Sasaki, Chiaki Takubo, Yoichi Hiruta
  • Patent number: 5508563
    Abstract: A semiconductor assembly comprises first and second containers which contain respective semiconductor chips and are stacked one over another. First and second external leads extending from the insides of the respective containers to outside thereof are bent so as to be connected to each other. The first and the second containers may be provided at corresponding positions with a recess and a projection to be engaged each other for positional alignment. There may be provided first and second heat radiating plates extending from the insides of the respective containers to outside thereof are bent so as to be connected to each other.
    Type: Grant
    Filed: September 28, 1994
    Date of Patent: April 16, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Tazawa, Chiaki Takubo, Yoshiharu Tsuboi, Mamoru Sasaki
  • Patent number: 5448451
    Abstract: Two device holes are formed in a base film such that the device holes are juxtaposed in a width direction of the base film perpendicular to a feed direction of the base film. An outer lead hole is formed in the base film with a distance from the device holes in the feed direction. A first lead wire group is arranged on the base film between the outer lead hole and one of the device holes, and a second lead wire group is arranged on the base film between the outer lead hole and the other device hole. Further, a third lead wire group is arranged on the base film between both device holes.
    Type: Grant
    Filed: November 19, 1993
    Date of Patent: September 5, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiaki Takubo, Kimihiro Ikebe, Masafumi Takeuchi, Seiichi Hirata, Sumio Takeda
  • Patent number: 5394010
    Abstract: A semiconductor assembly comprises first and second containers which contain respective semiconductor chips and are stacked one over another. First and second external leads extending from the insides of the respective containers to outside thereof are bent so as to be connected to each other. The first and the second containers may be provided at corresponding positions with a recess and a projection to be engaged each other for positional alignment. There may be provided first and second heat radiating plates extending from the insides of the respective containers to outside thereof are bent so as to be connected to each other.
    Type: Grant
    Filed: March 12, 1992
    Date of Patent: February 28, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Tazawa, Chiaki Takubo, Yoshiharu Tsuboi, Mamoru Sasaki
  • Patent number: 5304843
    Abstract: A semiconductor device, which uses a film carrier, comprises a semiconductor element with a plurality of terminals, a resin film with a first surface and a second surface, the film having a hole in which the semiconductor element is mounted, and a plurality of lead wires formed on the first surface of the resin film. Each lead wire has an inner lead, an intermediate lead and an outer lead. The inner lead is connected to a corresponding one of the terminals of the semiconductor element. The outer lead is connected to a corresponding external electrode. The intermediate lead is situated between the inner lead and the outer lead. At least said intermediate lead is formed on the first surface of the film. Each outer lead and that portion of the intermediate lead, which is close to the outer lead, is substantially on a level with the external electrode.
    Type: Grant
    Filed: September 21, 1992
    Date of Patent: April 19, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiaki Takubo, Hiroshi Tazawa, Yoshiharu Tsuboi, Masao Mochizuki
  • Patent number: 5220486
    Abstract: An IC packing device comprises a semiconductor device, a piece of flexible resin film provided with an opening for receiving the semiconductor, wires arranged on the piece of flexible resin film and slits cut into the piece of film from the edges of the opening. The slits cut into the flexible resin film allow the film to be flexed downward toward the semiconductor, along with the wires which to establish electrical connection with the semiconductor. In this manner, the downwardly bent flexible film provides reduction in the possibility of a wire breaking due to excessive bending of the wire in order to make contact with the semiconductor.
    Type: Grant
    Filed: September 11, 1991
    Date of Patent: June 15, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiaki Takubo, Hiroshi Tazawa, Yoshiharu Tsuboi
  • Patent number: 5162896
    Abstract: A tape-automated bonding substrate or TAB substrate used for mounting a gallium arsenide IC chip having external connection terminals including signal input and output terminals thereon is shown. Conductive thin-film wiring lines are formed on an insulative thin-film layer. These thin-film wiring lines include feed-through type signal input wiring lines to be connected to the input terminals of the chip. Each feed-through type signal input wiring line has an inner lead to which a corresponding signal input terminal of the chip is directly connected, a terminal pad for receiving a high-speed input signal, and a terminal pad to which an impedance-matching resistor is to be connected. The feed-through type signal input wiring lines have a composite line structure of micro-strip signal transmission and co-planar signal transmission line structures.
    Type: Grant
    Filed: February 7, 1991
    Date of Patent: November 10, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiaki Takubo, Kazutaka Saito, Toshio Sudo
  • Patent number: 5021866
    Abstract: A semiconductor integrated circuit device including first and second transmission leads formed on both sides of a resin film on which a semiconductor integrated circuit chip is mounted. These leads are connected at portions immediately close to the high-speed input terminals of the chip by through-hole leads. This chip-to-lead configuration according to the present invention is significantly effective for a GaAs logic integrated circuit or the like that processes high-speed input signals.
    Type: Grant
    Filed: September 28, 1988
    Date of Patent: June 4, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshio Sudo, Kazutaka Saito, Chiaki Takubo
  • Patent number: 4991001
    Abstract: There is disclosed a mounting structure for a semiconductor integrated circuit device or IC device having signal transmission terminals, which has an insulative substrate on which the IC device is mounted, a conductive signal transmission wiring line formed on the substrate and electrically connected to a selected one of the signal transmission terminals of the IC device, and an insulative resin layer formed on the substrate to at least partially cover the signal transmission wiring line. The insulative resin layer functions to change and set the impedance of the signal transmission wiring line to a desired impedance value. The insulative resin layer is formed to have a selected thickness such that the characteristic impedance of the wiring line, which tends to fluctuate in the wiring line etching formation process, can be adjusted and set towards a destination characteristic impedance.
    Type: Grant
    Filed: March 31, 1989
    Date of Patent: February 5, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiaki Takubo, Kazutaka Saito, Toshio Sudo
  • Patent number: 4949163
    Abstract: The semiconductor integrated circuit device of high speed operation can be obtained by adopting the feed-through termination system and by making the wiring pattern in that case as being of construction folded in the direction of thickness of the supporting circuit substrate, without increasing the housing density of the outer lead. In addition, since matching resistor is mounted on the external wall of the substrate, the manufacturing process is also simple without the making the outside dimensions of the substrate large.
    Type: Grant
    Filed: April 13, 1988
    Date of Patent: August 14, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshio Sudo, Chiaki Takubo
  • Patent number: 4926451
    Abstract: There is disclosed a digital integrated circuit device which has high-speed transistors of a selected type. A timing controller is incorporated in this device and performs timing control for an internal digital circuit. The timing controller includes a series-circuit of two flip-flop circuits serving as a frequency-dividing circuit for frequency-dividing a reference clock signal and generating an internal timing signal, and a switch circuit connected to a signal feedback line of these flip-flop circuits. In a normal mode, the switch circuit supplies the internal timing signal output from the flip-flop circuits to the digital integrated circuit. At a desired timing, the switch circuit performs a switching operation in response to a control signal, electrically disconnects the signal feedback line of the flip-flop circuits, and alternatively supplies an external timing signal externally supplied thereto to the digital integrated circuit.
    Type: Grant
    Filed: October 19, 1988
    Date of Patent: May 15, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kunio Yoshihara, Toshiyuki Terada, Chiaki Takubo, Nobuo Koide, Shoichi Shimizu