Abstract: When a resin 59 to form a molded body 20 is poured and a lead frame 30 is attached to a front end face 21 of the molded body 20 by insert molding, protective leads 32 provided on both outsides of a lead pattern 31 of the lead frame 30 moderate the flow of the resin 59 and the force acting on the lead pattern 31 is decreased, so that misregistration of the lead pattern 31 can be prevented. Accordingly, the inserted and molded lead frame 30 can be wired on the front end face 21 of the molded body 20 for easily accomplishing three-dimensional electric wiring.

Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.

Abstract: According to one aspect of the present invention, a semiconductor device, comprising a wiring board provided with wires and electrodes; a semiconductor element which is mounted on the wiring board and has plural connection electrodes formed on its surface; and a metal layer of fine metal particles aggregated and bonded which is interposed between the electrodes on the wiring board and the connection electrodes of the semiconductor element to connect between the electrodes and the connection electrodes, is provided.

Abstract: After a wiring plate 30 having a plurality of leads 31 been insert-molded to an edge face 21 of a molded article 20, unwanted portions of the wiring plate 30 are cut, thereby enabling easy three-dimensional wiring. As a result, an electrode terminal section 43 of a photoelectric conversion element 41 disposed opposite an end face 11b of an optical fiber 11 can be electrically coupled to an electrical wiring section 23 of an optical coupling part 10.

Abstract: A method for fabricating a semiconductor device includes mountain a first semiconductor chip on a wiring substrate, bonding a spacer having a first main surface and a second main surface opposing the first main surface such that the first main surface is in contact with the first semiconductor chip. The method further includes bonding a second semiconductor chip having a surface, onto the second main surface via a layer of a die bonding material selectively formed on a part of a third main surface.

Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.

Abstract: A wiring board comprises a substrate; a resin layer which is selectively formed on one main surface of the substrate and has fine metal particles contained or adhered to its surface; and a conductive metal layer which is formed on the resin layer with the fine metal particles interposed between them.

Abstract: Provided a semiconductor device including: a wiring board; a semiconductor chip having a pad electrically connected to a wiring on the wiring board; a second semiconductor chip provided on the wiring board at a position facing a side of the semiconductor chip, having passive elements integrated therein, and having pads for external connection to which both ends of the passive elements are connected respectively and at least one of which is electrically connected to the wiring on the wiring board electrically connected to the pad of the semiconductor chip.

Abstract: A semiconductor device includes a semiconductor substrate, a first wiring arranged on the semiconductor substrate, a first electrode pad electrically connected to the first wiring, and a porous organic resin film covering the front surface of the semiconductor substrate such that the first electrode pad is exposed to the outside.

Abstract: According to an embodiment of the present invention, a method of producing an electronic circuit comprises printing first metal-containing resin particles which consist of at least a thermosetting resin and fine metal particles and second metal-containing resin particles which consist of at least a thermoplastic resin and fine metal particles by electrophotography to form a first base pattern which consists of the first metal-containing resin particles and a second base pattern which consists of the second metal-containing resin particles on a substrate; forming a first metal conductor layer on the first and second base patterns; forming a second metal conductor layer on the first metal conductor layer by electrolytic plating by supplying electric current to the first metal conductor layer; and removing the second base pattern and the first and second metal conductor layers which are formed on the second base pattern.

Abstract: A wafer supporting plate is formed of a glass or a resin which can permeate ultraviolet rays and has a nearly disk shape. An outer diameter of the wafer supporting plate is larger than that of the semiconductor wafer which is supported. In the wafer supporting plate, a plurality of openings are formed to correspond to plural through holes of the semiconductor wafer. The opening has an open area larger than an open area of the through hole, that is, has a larger diameter.

Abstract: A semiconductor device which is compact and thin in size, low in resistance of a current path and parasitic inductance and excellent in reliability is provided. This semiconductor device comprises a semiconductor substrate, a first main electrode which is formed on a front surface of the semiconductor substrate, a second main electrode which is formed on a rear surface of the semiconductor substrate, and a conducting portion which is formed in a direction to pierce through the semiconductor substrate, wherein the second main electrode is extracted to the front surface of the semiconductor substrate via the conducting portion. And, the conducting portion is a through via which has a through hole formed through the semiconductor substrate in its thickness direction and a conductive portion which is formed in the through hole and connected to the second main electrode.

Abstract: A semiconductor device comprises a semiconductor substrate having an through hole, a first insulation resin layer formed on an inner surface of the through hole, a second insulation resin layer formed on at least one of front and rear surfaces of the semiconductor substrate, and a first conductor layer formed in the through hole to connect at least both front and rear surfaces of the semiconductor substrate and insulated from the inner surface of the through hole with the first insulation resin layer. A second conductor layer (wiring pattern) which is electrically connected to the first conductor layer in the through hole is further provided on the second insulation resin layer. The conductor layer formed in the through hole and constituting a connecting plug has a high insulation reliability. Therefore, a semiconductor device suitable for a multi-chip package and the like can be obtained.

Abstract: A plurality of signal processing semiconductor elements are stacked on or above a circuit board. A rewiring silicon chip is mounted on or above the circuit board. The rewiring silicon chip has an inner conductor layer for connection between the plural signal processing semiconductor elements and between the circuit board and the signal processing semiconductor elements. The circuit board and the plural signal processing semiconductor elements are electrically connected, and the plural signal processing semiconductor elements are electrically connected to each other. The interconnection of the plural signal processing semiconductor elements and the rearrangement of electrode pads of the signal processing semiconductor elements are realized by the rewiring silicon chip.

Abstract: According to an aspect of the present invention, there is provided an LSI package with an interface module including: an interposer, on which a signal processing LSI is mounted, having a mounting board connecting electrical terminal; and an interface module having a transmission line to wire a high-speed signal to the exterior and a socket connecting electrical terminal corresponding to a mounting board connecting socket, in which the interposer and the interface module have at least either loop electrodes or plate electrodes, respectively, and the interposer and the interface module are electrically connected by inductive coupling, electrostatic coupling, or combined coupling of these two couplings by at least either the loop electrodes or the plate electrodes.

Abstract: An optical semiconductor module comprises a guide which has a positioning portion for an optical transmission line, an optical semiconductor mounting surface from which one end face of the optical transmission line disposed in the positioning portion is exposed, and a wiring layer formed on the optical semiconductor mounting surface. An optical semiconductor element is mounted on the optical semiconductor mounting surface of the guide, with a light-emitting surface or a light-receiving surface thereof facing the one. end face of the optical transmission line, and is electrically connected to the wiring layer.

Abstract: A LSI package having an interface function with an exterior and a circuit device including the same comprises an interposer having a conductive terminal for connection to a mounting board, and an interface module which is electrically and mechanically connected to a surface of the interposer on which the conductive terminal is disposed, and interfaces signal input/output from/to the exterior and the interposer. Alternatively, the interface module is electrically and mechanically connected to a surface opposite a surface of the mounting board to which the interposer is connected.

Abstract: An organic semiconductor element comprises an organic semiconductor layer and an electrode supplying an electric current or an electric field to the organic semiconductor layer. The organic semiconductor layer includes a heat fusion layer of organic semiconductor particles. The heat fusion layer of the organic semiconductor particles is formed in such a manner that, for example, the organic semiconductor particles are made to adhere on a layer that is to be a base, by using an electrophotographic method, and thereafter, an adhesion layer of the organic semiconductor particles is heated to fusion bond the organic semiconductor particles. According to such an organic semiconductor element and a manufacturing method thereof, it is possible to enhance element manufacturing efficiency without an advantage of low cost and a miniaturization of an element structure.

Abstract: A method of manufacturing an electronic circuit satisfying demands for cost reduction, diversified small-quantity production, and a shorter cycle of design, manufacture, evaluation, correction, and so on is provided. The method includes at least forming a first pattern or forming a second pattern. Forming the first pattern comprises: forming a visible image on an electrostatic latent image formed on a photosensitive base, by the adhesion of charged particles essentially made of a resin; transferring the visible image onto the intermediate transfer base by the contact and pressurization of the visible image; heating/softening on the intermediate transfer base; and transferring a heated/softened resin layer onto a base material by the contact and pressurization of the resin layer.

Abstract: There is disclosed a semiconductor device comprising at least one semiconductor element, one chip mounting base being provided at least one first interconnection on one major surface thereof and at least one second interconnection on the other major surface thereof, and the semiconductor element being electrically connected to at least the one first interconnection and mounted on the one major surface, a sealing member being provided on the one major surface of the chip mounting base and covering the semiconductor element and the first interconnection, at least one third interconnection being provided on a surface of the sealing member, and at least one fourth interconnection being provided in the sealing member and the chip mounting base, and electrically connected to the first interconnection, the second interconnection, and the third interconnection.