Abstract: There is disclosed a semiconductor device which comprises a first chip-mounting substrate on which at least one semiconductor chip having a plurality of terminals is mounted, and a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, a second chip-mounting substrate which is laminated on the first chip-mounting substrate and on which at least one semiconductor chip is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a center offset from a center of a whole arrangement of the relay terminals.

Abstract: There is disclosed a laminated-chip semiconductor device which comprises two chip-mounting substrates on each of which at least one semiconductor chip having a plurality of terminals for signals is mounted, and a plurality of chip connecting wirings electrically connected to the terminals for signals of the each semiconductor chip which are mounted on the chip-mounting substrates are formed in a same pattern, and which are laminated along a thickness direction, and one intermediate substrate which is arranged between the two chip-mounting substrates, and in which a plurality of interlayer connecting wirings electrically connected to each of the plurality of chip connecting wirings of the adjacent chip-mounting substrate are formed in a predetermined wiring pattern.

Abstract: A multi-layer circuit board for mounting an electronic part such as a semiconductor chip having as many pins as 40×40 pins arranged as an array on the side of the mounting surface or a semiconductor device has a plurality of layers, each layer disposed one above another and containing lands arranged as an array disposed at an angle to the edge of the mounting surface. On each layer a plurality of the lands have connected thereto circuits extending from the lands to the edge of the mounting surface, and also lands not connected to circuits. Those lands not connected to circuits are connected with via holes to orther layers.

Abstract: A first via land of a wiring layer on a first surface of a first insulation layer that is a rigid layer and a second via land of a wiring layer on a second surface of a second insulation layer that is a flexible layer are electrically and mechanically connected with a conductive pillar pierced through a third insulation layer disposed between the first insulation layer and the second insulation layer. In such a structure, a wiring board that can mount a highly integrated semiconductor device, that is small and thin, and that has high reliability can be accomplished.

Abstract: A semiconductor device with a BGA package includes a substrate made of a resin and having one side on which a number of solder ball terminals are formed and the other side on which a chip mounting portion electrically connected to the solder ball terminals is formed, and a cover plate made of a metal and attached to a semiconductor chip so as to cover and come into contact with it under a condition where the semiconductor chip is connected to the resin substrate by a flip-chip process. The cover plate includes a base brought into contact with the semiconductor chip and a peripheral portion formed with a plurality of bonding portions where the cover plate is bonded to the substrate. The bonding portions are discontinuous to each other.

Abstract: Provided is a stacked type semiconductor device formed of a plurality of semiconductor integrated circuit devices stacked, each having a specification and including a semiconductor integrated circuit chip, wherein at least three of the semiconductor integrated circuit devices are stacked in the order of a value of the specification.

Abstract: A first via land of a wiring layer on a first surface of a first insulation layer that is a rigid layer and a second via land of a wiring layer on a second surface of a second insulation layer that is a flexible layer are electrically and mechanically connected with a conductive pillar pierced through a third insulation layer disposed between the first insulation layer and the second insulation layer. In such a structure, a wiring board that can mount a highly integrated semiconductor device, that is small and thin, and that has high reliability can be accomplished.

Abstract: A multi-layer circuit board having a decreased number of circuit boards for mounting an electronic part that has connection electrodes arranged in the form of an area array, featuring a high yield and improved reliability.

Abstract: The invention is concerned with a multi-layer circuit board for mounting an electronic part such as a semiconductor chip having as many pins as 40×40 pins arranged as an array on the side of the mounting surface or a semiconductor device having lands arranged like an array on the side of the mounting surface. The invention provides a multi-layer circuit board which makes it possible to mount an electronic part such as a semiconductor chip or a semiconductor device despite of a decreased number of circuit boards that are laminated one upon the other, which features improved yield of production, and which can be used as a highly reliable product.

Abstract: The invention is concerned with a multi-layer circuit board for mounting an electronic part such as a semiconductor chip having as many pins as 40×40 pins arranged as an array on the side of the mounting surface or a semiconductor device having lands arranged as an array on the side of the mounting surface. The invention provides a multi-layer circuit board with particular pad spacing and configuration which make it possible to mount an electronic part such as a semiconductor chip or a semiconductor device while reducing the number of circuit board layers that are laminated one upon the other.

Abstract: A first insulating film is formed on an integrated circuit chip on which an I/O pad is formed. A first opening portion is formed above the I/O pad. A conductive layer and a barrier metal layer which are electrically connected to the I/O pad through the first opening portion are stacked on the first insulating film. The conductive layer and the barrier metal layer are patterned by a single mask. A second insulating film is formed on the resultant structure. A second opening portion is formed in the second insulating film at a position different from that of the first opening portion. A solder bump or metal pad is formed on the barrier metal layer in the second opening portion. The position of the solder bump or metal pad is defined by the second opening portion.

Abstract: A board body constituting a characteristic evaluation board has a holding section for holding a semiconductor chip therein. The semiconductor chip has a plurality of bumps. The respective bumps of the semiconductor chip are set in contact with corresponding electrodes with the semiconductor chip held in the holding section in the board body. Clamping mechanisms are located on the surface of the board body in the neighborhood of the holding section. The clamping mechanisms press the semiconductor chip held in the holding section. The respective bumps on the semiconductor chip are pressure contacted with the corresponding electrodes. Since the respective bumps are pressure contacted with the corresponding electrodes without using a solder, the respective bumps can be formed of an eutectic solder. The semiconductor chip held in the holding section can readily be taken out of the holding section by opening the clamping mechanisms.

Abstract: Disclosed is an apparatus and method for inspecting a connection state of a lead electrode to a bump after TAB (tape automated bonding). An LSI chip is immobilized on a stage. A flexible lead is held by a holding portion and connected to a bump. Above the chip, a CCD camera is provided. The stage is controlled to move up and down by a moving control mechanism. Each of the lead/bump connection states immediately after ILB (Inner lead bonding) is taken in the form of image data and defined as a first image data. A second image data of the lead/bump connection state is taken after the bump and lead are moved to different positions by moving the stage in order to change the position of the chip by means of the moving control mechanism. Whether or not the lead is duly connected to the bump is determined by the comparison of the first and second image data.

Abstract: A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated Sn layer formed on the Cu core, and the bonding part is formed of an Au-rich Au--Cu--Sn alloy of a ternary system having a single-phase structure containing 15 at. % or less Sn and 25 at. % or less Cu.

Abstract: The present invention is characterized by providing leads not contributing to actual connection outside the corner leads to prevent the deformation of the corner leads and improve the yield of tape carriers. A device hole is made in a near-central place of an insulating resin film. Around the device hole, outer-lead holes are made. On the insulating resin film, a plurality of wiring patterns are provided and forced to project into the device hole. The plurality of wiring patterns are formed into a plurality of inner leads, of which the outermost ones are determined to be corner leads. On each corner of the device hole, an aligning mark is provided. Dummy leads are provided closer to the aligning marks. The dummy leads are made shorter than the inner leads and corner leads.

Abstract: In a flip chip mounting type semiconductor device, on a corner portion of a chip subjected to flip chip mounting, a gate region for injecting a sealing member filled between a mounted board and the chip is arranged. In this semiconductor device, a semiconductor element has a plurality of bumps formed on the peripheral portion on a major surface along each side, a plurality of pad electrodes are formed on the major surface of the circuit board, and the pad electrodes join the bumps. A resin sealing member is filled between the semiconductor element and the circuit board. A gate region through which the resin sealing member is injected is formed on a corner portion of the semiconductor element. In the gate region, no bump is formed, or bumps are arranged at intervals smaller than that in another region. For this reason, the resin uniformly enters the space between the semiconductor element and the circuit board through the gate region.

Abstract: A semiconductor device having bump electrodes, each having a structure wherein an alloy layer such as Au--Sn formed by the reaction between the Sn-plated layer on the surface of the inner lead and the bump electrode never reach the bottom surface of the passivation opening portion, is provided. The center of the passivation opening portion is displaced apart from the center of an electrode pad to a direction toward the center of the semiconductor substrate. The center of the passivation opening portion is displaced away from the outer lead and close to the tip end of the inner lead in contrast to the center of the bump electrode. By positioning the passivation opening portion such that the center thereof is located nearer to the center of semiconductor substrate than a center of the bump electrode, without changing the height of the bump electrode or the size of the passivation opening portion, the Au--Sn alloy etc.

Abstract: A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated Sn layer formed on the Cu core, and the bonding part is formed of an Au--rich Au--Cu--Sn alloy of a ternary system having a single-phase structure with a composition of 15 atomic % Sn or less and 25 atomic % Cu or less.

Abstract: A display device comprising a substrate, a rectangular display section provided on the substrate and having four sides, a plurality of driving semiconductor elements formed on peripheral portions of the substrate in the vicinity of the display section, each of the driving semiconductor elements having two opposite long sides and two opposite short sides, one of the two long sides being opposed to one side of the display section, a plurality of output lines extending from the one long side of each of the driving semiconductor elements to the display section, to output signals from the driving semiconductor elements to the display section, a plurality of input lines extending from both the short sides of each of the driving semiconductor elements, to input signals to the driving semiconductor elements to drive them, a plurality of output terminals formed on each of the driving semiconductor elements along both the long sides thereof, and electrically connected to the output lines, the number of the output termi

Abstract: A semiconductor device having a bump electrode includes a first conductive layer formed on a predetermined portion of a substrate. An insulating layer is formed on the substrate and the first conductive layer. The insulating layer has an opening portion such that a predetermined portion of the first conductive layer is exposed. A second conductive layer is formed on the first conductive layer, a side wall of the opening portion of the insulating layer, and an upper surface of the insulating layer. A third conductive layer is formed to cover at least the insulating layer on the first conductive layer and the second conductive layer along the portion. A fourth conductive layer is formed on the third conductive layer to have an over hang portion. A side etch portion is formed surrounded with an over hang portion of the fourth conductive layer, the third conductive layer, and the insulating layer.