Abstract: A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.

Abstract: A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A touch module includes a base plate, a magnet, a touchpad and a magnetic board. The magnetic board includes a first sensing line, a second sensing line, a third sensing line, a first communication part and a second communication part. The touchpad is located over the base plate. The magnetic board is arranged between the touchpad and the magnet. The first sensing line, the second sensing line and the third sensing line of the magnetic board are in parallel with each other and stacked on each other. The first sensing line is electrically connected with the second sensing line through the first communication part. The second sensing line is electrically connected with the third sensing line through the second communication part. The first sensing line, the second sensing line and the third sensing line sense a magnetic field of the magnet and generates a vibration.

Abstract: A method of patterning an underlying structure includes the following. A first patterning process is performed on the underlying structure to form a first patterned underlying structure including a first opening. A patterned photoresist layer is formed, and the patterned photoresist layer fills the first opening. A second patterning process is performed on the first patterned underlying structure to form a second patterned underlying structure including the first opening and a second opening.

Abstract: Provided is a semiconductor device including a substrate having a lower portion and an upper portion on the lower portion; an isolation region disposed on the lower portion of the substrate and surrounding the upper portion of the substrate in a closed path; a gate structure disposed on and across the upper portion of the substrate; source and/or drain (S/D) regions disposed in the upper portion of the substrate at opposite sides of the gate structure; and a channel region disposed below the gate structure and abutting between the S/D regions, wherein the channel region and the S/D regions have different conductivity types, and the channel region and the substrate have the same conductivity type.

Abstract: A touchpad module includes a base plate, a touch member and at least one pressure sensing module. The touch member is located over the base plate. The touch member includes a touch plate and a touch sensitive circuit board. The pressure sensing module is arranged between the base plate and the touch member. The pressure sensing module includes a pressure sensor and a miniature supporting plate. The pressure sensor is installed on the miniature supporting plate. The pressure sensor is electrically connected with the touch sensitive circuit board through the miniature supporting plate. While the touch member is pressed in response to an external pressing force, the pressing force exerted on the touch member is sensed by the at least one pressure sensing module, and the pressure sensing module generates a pressure sensing signal.

Abstract: A semiconductor package includes a first semiconductor die and a second semiconductor die disposed laterally adjacent one another. The semiconductor package includes a semiconductor bridge overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. The semiconductor bridge electrically couples the first semiconductor to the second semiconductor die. The semiconductor package includes a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively. The semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die.

Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.

Abstract: An Image Activated Cell Sorting (IACS) classification workflow includes: employing a neural network-based feature encoder (or extractor) to extract features of cell images; automatically clustering cells based on extracted cell features; identifying a cluster to pick which cluster(s) to sort based on the cell images; fine-tuning a classification network based on the cluster(s) selected; and once refined, the classification network is used to sort cells for real-time live sorting.

Abstract: A foldable electronic device includes a first body, a second body, a pivot and a key module. The pivot is pivotally connected between the first body and the second body. The first body and the second body is configured to rotate relatively to each other through the pivot. The key module includes a bendable substrate and a sensor embedded in the bendable substrate. The bendable substrate is connected between the first body and the second body and covers an outer side of the pivot. The sensor generates a sensing signal in response to a press of a user upon the bendable substrate.

Abstract: A package structure, including: a first packaging member having oppositely arranged first surface and second surface; a control chip covered by the first packaging member; a plurality of conductors provided on and protruding from the control chip and electrically connected to electrical contacts of the control chip, the conductors being covered by the first packaging member, and ends of the conductors facing away from the control chip being flush with the first surface; a wire pattern layer disposed on the first surface and electrically connected to the conductors; a light emitting element located on the first surface and electrically connected to the control chip via the wire pattern layer; and a second packaging member covering the light emitting element and affixed to the first surface and the wire pattern layer, a light beam emitted by the light emitting element being allowed to travel outward through the second packaging member.

Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

Abstract: A semiconductor device includes an analog voltage regulator and an integrated circuit module. The analog voltage regulator generates a regulated output voltage. The integrated circuit module generates an analog sense voltage based on the regulated output voltage and includes integrated circuit dies, a first sensor, second sensors, and a digital voltage offset controller (DVOC). The first sensor generates a digital reference voltage based on an analog reference voltage. The second voltage sensors detect voltages at predetermined locations on the integrated circuit dies. The DVOC generates a digital offset voltage substantially equal to the difference between the digital reference voltage and the voltage detected by a selected one of the second voltage sensors. The regulated output voltage is based on an unregulated input voltage, the analog sense voltage, and the digital offset voltage.

Abstract: An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.

Abstract: A bonded assembly includes an interposer; a semiconductor die that is attached to the interposer and including a planar horizontal bottom surface and a contoured sidewall; a high bandwidth memory (HBM) die that is attached to the interposer; and a dielectric material portion contacting the semiconductor die and the interposer. The contoured sidewall includes a vertical sidewall segment and a non-horizontal, non-vertical surface segment that is adjoined to a bottom edge of the vertical sidewall segment and is adjoined to an edge of the planar horizontal bottom surface of the semiconductor die. The vertical sidewall segment and the non-horizontal, non-vertical surface segment are in contact with the dielectric material portion. The contoured sidewall may provide a variable lateral spacing from the HBM die to reduce local stress in a portion of the HBM die that is proximal to the interposer.

Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.

Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.

Abstract: An antenna structure includes a first substrate and a second substrate. The first substrate includes: a semiconductor chip configured to transmit or receive a first radio-frequency (RF) signal; a first ground layer configured to provide ground to the semiconductor chip; and a signal layer arranged on a side of the first substrate opposite to the semiconductor chip and configured to transmit the first RF signal. The second substrate has an antenna array formed of antenna cells, each of the antenna cells including: a first antenna layer configured to radiate second RF signals based on the first RF signal; a second ground layer configured to provide ground to the first antenna layer. The antenna device further includes a plurality of connectors electrically coupling the semiconductor chip to the antenna array.

Abstract: A memory access speed adjustment method, control device and memory module are provided. The method is for use in controlling a controller of a memory and includes steps of: obtaining a current temperature value of the memory; determining an access speed threshold of the memory according to a continuous variation relation with respect to a difference between the current temperature value and a target temperature value; and adjusting, by the controller, an access speed of the memory according to the access speed threshold.