Abstract: A head mounted display device and a power management method are provided. The head mounted display device includes a host part and a power input part. The power input part is detachably connected to a power device and an electronic device. The power input part generates a first input signal according to a supply voltage value of the power device, and generates a second input signal according to power supply information of the electronic device. The host part enters a power saving mode or performs a boot-up operation according to the first input signal and the second input signal.

Abstract: Systems and methods for intelligent fan identification are described. In some embodiments, an Information Handling System (IHS) may include: an embedded controller (EC); and a memory coupled to the EC, the memory having program instructions stored thereon that, upon execution by the EC, cause the IHS to: detect a cooling fan configuration issue; determine that a number of cooling fans in the IHS has not changed between a previous configuration and a current configuration; and in response to the determination, abstain from identifying the cooling fan configuration issue as a cooling fan error.

Abstract: Disclosed herein are related to an integrated circuit including multiple dies stacked along a direction. In one aspect, the integrated circuit includes a first die, a second die, and a third die stacked along the direction. In one aspect, the first die includes a first interface circuit to generate a signal. In one aspect, the second die includes a second interface circuit to receive the signal from the first interface circuit and generate a replicate signal of the signal. In one aspect, the third die includes a third interface circuit to receive the replicate signal from the second interface circuit.

Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.

Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

Abstract: A touchpad module includes a bracket, a touch member and a supporting plate. The supporting plate is arranged between the bracket and the touch member. When an end of the touch member is pressed down, the end of the touch member is swung relative to the bracket through the supporting plate. The supporting plate includes a plate body, at least one supporting part and a swingable part. The plate body, the at least one supporting part and the swingable part are integrally formed as a one-piece structure. The present invention further provides a computing device with the touchpad module.

Abstract: A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode.

Abstract: Methods, systems, and computer program products are described for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor device design. These netlists provide RTL design information corresponding to a portion of a semiconductor device. A configuration tracer generates behavior information associated with the RTL design. A register compiler compiles a set of semiconductor devices based on one or more technologies and power, performance, and area (PPA) information related to the semiconductor device. Semiconductor devices generated by the register compiler that meet predefined power, performance, and area conditions are identified. Structural information for aligning the input/output ports of the semiconductor device is generated.

Abstract: A light source module includes a transparent conductive substrate, a circuit assembly and a light-emitting element. The circuit assembly is electrically connected with a conductive film of the transparent conductive substrate. The circuit assembly includes a feed terminal. The feed terminal is coupled with a po-go pin. The light-emitting element is installed on the conductive film of the transparent conductive substrate. The present invention also provides a computing device with the light source module.

Abstract: Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.

Abstract: Systems and methods for intelligent fan identification are described. In some embodiments, an Information Handling System (IHS) may include: an embedded controller (EC); and a memory coupled to the EC, the memory having program instructions stored thereon that, upon execution by the EC, cause the IHS to: detect a cooling fan configuration issue; determine that a number of cooling fans in the IHS has not changed between a previous configuration and a current configuration; and in response to the determination, abstain from identifying the cooling fan configuration issue as a cooling fan error.

Abstract: A solar adjustment apparatus includes a control circuit, two optical encoders, two driving modules, and a power circuit. The control circuit is arranged in an upper rail, and the upper rail is fixed on the upper side of a door or window of a building or vehicle. The two driving modules pivot two spools at the same speed. One of the driving modules controls a height of a middle rail in vertical direction of the door or window through one of optical encoders and one of spools. The other driving module controls a height of a lower rail in vertical direction of the door or window through the other optical encoder and the other spool.

Abstract: A device for power estimation is disclosed. The device includes a transformer circuit coupled with a processing circuit and a transaction interface. The transformer circuit is configured to count performance activities executed in the processing circuit and to compare count values of the performance activities with a predetermined value to determine a power state of the processing circuit. The transaction interface is configured to receive a request from the processing circuit and record a first timestamp, and further configured to receive a response from a memory model and record a second timestamp, the transaction interface being further configured to record a time difference between the first timestamp and the second timestamp as a time difference. The transformer circuit is further configured to determine the power state of the processing circuit based on both of the count values and the time difference.

Abstract: A method for deploying a computer operating environment and a deployment system are provided. A template machine is provided. A deployment program is executed in the template machine for scanning data of an operating system and applications in the template machine. The data are segmented into multiple segments and then encoded. An index and a checksum for each of the segments called metainfo are created. The metainfo is distributed to terminal machines within a network domain. After receiving the metainfo, every terminal machine obtains the segments, decodes the segments, and verifies the correctness of the received segments with the checksum. When requested by other terminal machines, the terminal machine reads the specific segments and then distributes those to the other terminal machines via a peer-to-peer data sharing protocol. The deployment is completed after all of the segments of operating environment are written in the terminal machine.

Abstract: An interface for a semiconductor device includes a master device and a plurality of slave devices. The interface includes a master interface and a slave interface. The master interface is implemented in the master device and includes a master bond pattern of master bonds arranged as a first array. The slave interface is implemented each slave device and includes a slave bond pattern of slave bonds arranged as a second array. The first array of the master bonds includes a first central row and first data rows in two parts being symmetric to the first central row. The second array of the slave bonds includes a second central row and second data rows in two parts being symmetric to the second central row. The first central row and the second central row are aligned in connection, and the first data rows are connected to the second data rows.

Abstract: A light source module includes a supporting substrate, plural light-emitting unit and a light mixing structure. The light mixing structure is disposed on the supporting substrate. The light mixing structure includes plural crooked light mixing channels. After the light beams emitted by the light-emitting unit are introduced into the corresponding light mixing channel, the light beams are mixed together in the corresponding light mixing channel, and the mixed light beams are outputted from the corresponding light mixing channel. Moreover, an electronic device with the light source module is provided.

Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

Abstract: An electronic device includes a package structure with opposite first and second sides spaced apart along a first direction, opposite third and fourth sides spaced apart along a second direction, opposite fifth and sixth sides spaced apart along a third direction, the first, second, and third directions being orthogonal to one another. A set of first leads extend outward from the first side along the first direction, a set of second leads extend outward from the second side along the first direction, and a thermal pad includes a first portion that extends along a portion of the fifth side, and a second portion that extends along a portion of the third side to facilitate cooling and visual solder inspection when soldered to a host printed circuit board.

Abstract: A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.