Abstract: Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.

Abstract: A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode.

Abstract: Disclosed herein are related to an integrated circuit including multiple dies stacked along a direction. In one aspect, the integrated circuit includes a first die, a second die, and a third die stacked along the direction. In one aspect, the first die includes a first interface circuit to generate a signal. In one aspect, the second die includes a second interface circuit to receive the signal from the first interface circuit and generate a replicate signal of the signal. In one aspect, the third die includes a third interface circuit to receive the replicate signal from the second interface circuit.

Abstract: A semiconductor package includes a first die comprising a voltage regulator that has a first input and a second input. The semiconductor package includes a second die coupled to the first die and comprising a first load circuit. The voltage regulator is configured to provide a regulated voltage to the first load circuit through a first through via structure based on a first voltage received through the first input and a second voltage received from the first load circuit through a second through via structure. The first voltage is a constant reference voltage, and the second voltage is a first signal sensed from the first load circuit.

Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

Abstract: A touchpad module includes a base plate, a touch member, plural supporting elements, plural pressure sensing units and a feedback generation element. The base plate includes a plate body and plural elastic arms. The plural elastic arms are formed on the plate body. The plural supporting elements are arranged between the base plate and the touch member, and aligned with the corresponding elastic arms. While the touch member is moved toward the base plate, the plural supporting elements are move downwardly with the touch member to press the corresponding elastic arms. Consequently, the plural elastic arms are subjected to deformation. If the deformation amount of at least one of the plural elastic arms reaches a threshold value, the corresponding pressure sensing unit issues a pressure sensing signal. The feedback generation element generates a haptics feedback effect in response to the pressure sensing signal.

Abstract: An integrated circuit includes first through fourth devices positioned over one or more substrates, a first radio frequency interconnect (RFI) including a first transmitter included in the first device, a first receiver included in the second device, and a first guided transmission medium coupled to each of the first transmitter and the first receiver, a second RFI including a second transmitter included in the first device, a second receiver included in the third device, and a second guided transmission medium coupled to each of the second transmitter and the second receiver, and a third RFI including a third transmitter included in the first device, a third receiver included in the fourth device, and the second guided transmission medium coupled to each of the third transmitter and the third receiver.

Abstract: A light guide structure for a backlight module is provided. A light source of the backlight module emits a light beam. The light beam is guided by the light guide structure. The light guide structure includes a plate body and a light-shielding layer. The plate body includes a light-transmissible plate, a light-guiding plate and a reflecting plate. The light-guiding plate has a lateral surface. The light-transmissible plate has a light-transmissible plate lateral surface. The reflecting plate has a reflecting plate lateral surface. The lateral surface of the light-guiding plate, the light-transmissible plate lateral surface and the reflecting plate lateral surface are collaboratively formed as a plate body lateral surface. The plate body lateral surface is covered by the light-shielding layer. The light beam from the light source is blocked by the light-shielding layer.

Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.

Abstract: A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.

Abstract: A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.

Abstract: An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.

Abstract: Disclosed herein are related to an integrated circuit including multiple dies stacked along a direction. In one aspect, the integrated circuit includes a first die, a second die, and a third die stacked along the direction. In one aspect, the first die includes a first interface circuit to generate a signal. In one aspect, the second die includes a second interface circuit to receive the signal from the first interface circuit and generate a replicate signal of the signal. In one aspect, the third die includes a third interface circuit to receive the replicate signal from the second interface circuit.

Abstract: A horizontal assembly press apparatus for performing a press-fit operation of a workpiece assembly along a horizontal axis includes a machine body unit, two moving units, two camera units, two pressing bed units and a processing unit. The machine body unit includes two main machine bodies defining an operating channel therebetween. The moving units are respectively and movably disposed on the main machine bodies. The camera units fetch images of the workpiece assembly entered the operating channel and output image signals. The pressing bed units are operated to press the workpiece assembly. The processing unit receives and analyzes the image signals, determines a target position of the horizontal axis, controls movement of the moving units to bring the pressing bed units to the target position, and controls movement of the pressing bed units to perform the press-fit operation of the workpiece assembly.

Abstract: A touchpad module includes a touch member, a base plate, a supporting element and a switch. The touch member includes a first touch region and a second touch region. The base plate is located under the touch member. The supporting element is arranged between the touch member and the base plate. The supporting element is aligned with the second touch region. The switch is arranged between the touch member and the base plate. The switch is aligned with the second touch region. When a pressing force is applied to the second touch region of the touch member, the pressing force is transmitted to the base plate through the supporting element. Consequently, the base plate is subjected to deformation. The switch is triggered in response to the deformation of the base plate.

Abstract: A voltage regulator includes an output node, a control circuit, and a power stage. The control circuit is configured to receive a power state signal from a load circuit coupled to the output node, and output a control signal based on the power state signal. The power stage includes a plurality of phase circuits coupled to the output node and is configured to enable a phase circuit of the plurality of phase circuits responsive to the control signal.

Abstract: A touch module includes a base plate, a magnet, a touchpad and a magnetic board. The magnetic board includes a first wiring layer, a second wiring layer and a third wiring layer. The magnet is installed on the base plate. The touchpad is located over the base plate. The magnet is covered by the touchpad. The magnetic board is arranged between the touchpad and the magnet. The first wiring layer, the second wiring layer and the third wiring layer are in parallel with each other and stacked on each other. The second wiring layer is arranged between the first wiring layer and the third wiring layer. The first wiring layer is connected with the second sensing line through the third wiring layer. The first sensing line, the second sensing line and the third sensing line sense a magnetic field of the magnet and generates a vibrating effect.

Abstract: An integrated circuit includes a first through fourth devices positioned over a substrate, the first device including first through third transceivers, the second device including a fourth transceiver, the third device including a fifth transceiver, and the fourth device including a sixth transceiver. A first radio frequency interconnect (RFI) includes the first transceiver coupled to the fourth transceiver through a first guided transmission medium, a second RFI includes the second transceiver coupled to the fifth transceiver through a second guided transmission medium, and a third RFI includes the third transceiver coupled to the sixth transceiver by the second guided transmission medium.