Patents by Inventor Chiang Huang

Chiang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11918387
    Abstract: An infant care apparatus includes a piezoelectric sensor and an infrared array sensor. The piezoelectric sensor senses a respiration rate and a heart rate of an infant. The infrared array sensor senses a body temperature and an occupancy state of the infant in a non-contact manner. The abovementioned infant care apparatus can assist in determining an abnormality of the respiration rate and the heart rate of the infant based on the occupancy state of the infant output by the infrared array sensor, so as to reduce a false alarm rate.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: March 5, 2024
    Assignee: ORIENTAL SYSTEM TECHNOLOGY INC.
    Inventors: Chein-Hsun Wang, Chun-Chiang Chen, Wen-Chie Huang, Ming Le
  • Publication number: 20240072034
    Abstract: A method includes bonding a first device die to a second device die through face-to-face bonding, wherein the second device die is in a device wafer, forming a gap-filling region to encircle the first device die, performing a backside-grinding process on the device wafer to reveal a through-via in the second device die, and forming a redistribution structure on the backside of the device wafer. The redistribution structure is electrically connected to the first device die through the through-via in the second device die. A supporting substrate is bonded to the first device die.
    Type: Application
    Filed: January 9, 2023
    Publication date: February 29, 2024
    Inventors: Ching-Yu Huang, Kuo-Chiang Ting, Ting-Chu Ko
  • Publication number: 20240071138
    Abstract: A computing apparatus, method, and non-transitory computer readable storage medium thereof are provided. The apparatus receives a plurality of character motion data of a plurality of virtual characters. The apparatus classifies the virtual characters based on the character motion data to generate a plurality of frame update groups, and each of the frame update groups corresponds to a motion calculation period. At each frame, the apparatus selects one of at least one subset of each of the frame update groups to calculate a motion synthesis for each of the virtual characters.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: Sheng-Jie LUO, Chi-Chiang HUANG
  • Publication number: 20240069636
    Abstract: A touch device includes a touch panel, a circuit board, a vibrating unit and a pressure detection module. The touch panel includes two press regions. When different press regions of the touch panel are pressed by the user, the vibration feedback values generated by different press regions are different.
    Type: Application
    Filed: September 14, 2022
    Publication date: February 29, 2024
    Inventors: Chieh-Hung Hsieh, Wei-Chiang Huang, Chao-Wei Lee, Hsueh-Chao Chang, Sian-Yi Chiu
  • Patent number: 11916146
    Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
  • Patent number: 11907428
    Abstract: A touch device includes a touch panel, a circuit board, a vibrating unit and a pressure detection module. The touch panel includes two press regions. When different press regions of the touch panel are pressed by the user, the vibration feedback values generated by different press regions are different.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: February 20, 2024
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Chieh-Hung Hsieh, Wei-Chiang Huang, Chao-Wei Lee, Hsueh-Chao Chang, Sian-Yi Chiu
  • Publication number: 20240053857
    Abstract: A touch module includes a base plate, a magnet, a touchpad and a magnetic board. The magnetic board includes a first sensing line, a second sensing line, a third sensing line, a first communication part and a second communication part. The touchpad is located over the base plate. The magnetic board is arranged between the touchpad and the magnet. The first sensing line, the second sensing line and the third sensing line of the magnetic board are in parallel with each other and stacked on each other. The first sensing line is electrically connected with the second sensing line through the first communication part. The second sensing line is electrically connected with the third sensing line through the second communication part. The first sensing line, the second sensing line and the third sensing line sense a magnetic field of the magnet and generates a vibration.
    Type: Application
    Filed: May 31, 2023
    Publication date: February 15, 2024
    Inventors: Hung-Wei Kuo, Tse-Ping Kuan, Ying-Yen Huang, Wei-Chiang Huang
  • Publication number: 20240053827
    Abstract: A touch feedback correction method and a touch module using the touch feedback correction method are provided. In the touch feedback correction method, the coordinate values and the initial vibration values of plural press region on a touch panel of the touch module are detected. Consequently, a driving voltage calibration table is established. Then, a vibrating unit of the touch module is driven according to plural compensated voltage values of the driving voltage calibration table. Consequently, the plural press regions generate plural corrected vibration values, respectively.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 15, 2024
    Inventors: Chieh-Hung Hsieh, Wei-Chiang Huang, Chao-Wei Lee, Chun-Pi Wang, Hsueh-Chao Chang, Sian-Yi Chiu
  • Patent number: 11899857
    Abstract: A touchpad module includes a base plate, a touch member, a supporting structure and a pressure sensing unit. The touch member is movable toward the base plate. The supporting structure is arranged between the base plate and the touch member. The pressure sensing unit is installed on the touch member. The pressure sensing unit is arranged between the touch member and the base plate. While the touch member is pressed in response to an external pressing force, the touch member is moved downwardly toward the base plate to compress the supporting structure. Consequently, the supporting structure is subjected to deformation, and the touch member has a displacement amount. According to the displacement amount, a magnitude of the pressing force is sensed by the pressure sensing unit, and a pressure sensing signal is outputted from the pressure sensing unit.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: February 13, 2024
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Wei-Chiang Huang, Hung-Wei Kuo, Chao-Wei Lee, Chen-Yu Wu
  • Publication number: 20240019915
    Abstract: A computer-implemented method of managing a thermal policy of an information handling system involves identifying a first power associated with a central processing unit (CPU) of the information handling system, identifying a first time duration of a first workload associated with the CPU, accessing a table indicating, for combinations of workload time durations and CPU power, a ramp rate and a thermal management mode, comparing the first power and the first time duration with the table to identify a first ramp rate and a first thermal management mode associated with the first power and the first time duration, and placing the CPU and a fan of the information handling system in the first thermal management mode and adjusting a fan speed of the fan based on the first ramp rate.
    Type: Application
    Filed: July 18, 2022
    Publication date: January 18, 2024
    Inventors: TseAnGino Chu, Ting-Chiang Huang, Chung-Wei Wang, Qinghong He
  • Publication number: 20240012969
    Abstract: A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.
    Type: Application
    Filed: June 5, 2023
    Publication date: January 11, 2024
    Inventors: Haohua Zhou, Tze-Chiang Huang, Mei Hsu Wong
  • Publication number: 20240006249
    Abstract: The present disclosure provides an electronic device including a redistribution layer, a plurality of passive components, and an electronic component. The redistribution layer includes a first insulating layer, a second insulating layer, and a plurality of traces electrically connected to each other through a first opening of the first insulating layer and a second opening of the second insulating layer, wherein the first insulating layer has a first side away from the second insulating layer, and the second insulating layer has a second side away from the first insulating layer. The passive components are disposed on the first side. The electronic component is disposed on the second side. The plurality of passive components are electrically connected to the electronic component through the plurality of traces.
    Type: Application
    Filed: September 19, 2023
    Publication date: January 4, 2024
    Applicant: InnoLux Corporation
    Inventors: Yeong-E CHEN, Kuang-Chiang HUANG, Yu-Ting LIU, Yi-Hung LIN, Cheng-En CHENG
  • Patent number: 11862538
    Abstract: In some examples a semiconductor chip package includes a conductive terminal. In addition, the semiconductor chip package includes a die pad including a top side and a recess extending into the top side. The die pad is downset relative to the conductive terminal. Further, the semiconductor ship package includes a semiconductor die positioned within the recess, wherein the semiconductor die has an outer perimeter, and a solder fillet engaged within the recess and with the outer perimeter of the semiconductor die. Still further, the semiconductor chip package includes a wire bond coupled to the semiconductor die and the conductive terminal, and a mold compound covering the conductive terminal, the wire bond, the die pad, and the semiconductor die.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chung-Hao Lin, Hung-Yu Chou, Bo-Hsun Pan, Dong-Ren Peng, Pi-Chiang Huang, Yuh-Harng Chien
  • Patent number: 11854943
    Abstract: An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: December 26, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Hidehiro Fujiwara, Tze-Chiang Huang, Hong-Chen Cheng, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yun-Han Lee, Lee-Chung Lu
  • Publication number: 20230366917
    Abstract: Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Haohua Zhou, Mei Hsu Wong, Tze-Chiang Huang
  • Publication number: 20230343754
    Abstract: A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: Haohua Zhou, Mei Hsu Wong, Tze-Chiang Huang
  • Publication number: 20230338843
    Abstract: An image processing method for a game loop of a game, wherein the game loop comprises a game rendering module and a MEMC module, and is executed by more than one processing unit to generate an output image to display. The image processing method includes rendering, by the game rendering module, a scene of the game to obtain a first image; rendering, by the game rendering module, a UI to obtain a second image; applying, by the MEMC module, MEMC to the first image to generate an interpolated first image; and blending, by the MEMC module, the second image and the interpolated first image into the output image.
    Type: Application
    Filed: April 18, 2023
    Publication date: October 26, 2023
    Applicant: MEDIATEK INC.
    Inventors: Tsung-Shian Huang, Huei-Long Wang, Yan-Hong Zhang, Chi-Chiang Huang, Kuo-Yi Wang, An-Li Wang, Chien-Nan Lin
  • Patent number: 11798853
    Abstract: The present disclosure provides a manufacturing method of a package device, which includes providing a carrier substrate, a first conductive layer, and a release layer, where the carrier substrate has a device region and a peripheral region, and the first conductive layer and the release layer are disposed on the carrier substrate. The method further includes forming a second conductive layer on the release layer in the device region, where at least one of the first and second conductive layers includes a first pad in the peripheral region. The second conductive layer includes a second pad electrically connected to the first pad through the first conductive layer. The method also includes performing an inspection step to provide an input signal to one of the first and second pads, and to receive an output signal from another of the first and second pads.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: October 24, 2023
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Kuang-Chiang Huang, Yu-Ting Liu, Yi-Hung Lin, Cheng-En Cheng
  • Publication number: 20230310320
    Abstract: The present disclosure provides a soluble microcarrier, including soluble polymer including a plurality of soluble monomers binding to each other with a reducing crosslinking agent. The soluble microcarrier of present disclosure facilitates the attachment of cells, and reducing agents can facilitate the detachment of cells. When the soluble microcarrier is in contact with a reducing agent, the soluble microcarrier degrades.
    Type: Application
    Filed: May 11, 2022
    Publication date: October 5, 2023
    Inventors: Hsieh-Chih TSAI, Shuian-Yin LIN, Ming-Chien YANG, Chun-Chiang HUANG, Yu-Hsuan LIN
  • Publication number: 20230299678
    Abstract: A voltage regulator includes a control circuit configured to output a plurality of enable signals, and a power stage including a plurality of phase circuits. Each phase circuit of the plurality of phase circuits includes a node, an inductor coupled between the node and an output node of the voltage regulator, a plurality of p-type transistors coupled between the node and a power supply node of the voltage regulator, and a plurality of n-type transistors coupled between the node and a reference node of the voltage regulator. Each phase circuit of the plurality of phase circuits is configured to, responsive to the plurality of enable signals, selectively couple the node to the power supply node through a first subset or all of the plurality of p-type transistors, and selectively couple the node to the reference node through a second subset or all of the plurality of n-type transistors.
    Type: Application
    Filed: April 18, 2023
    Publication date: September 21, 2023
    Inventors: Haohua ZHOU, Tze-Chiang HUANG, Mei HSU, Yun-Han LEE