Patents by Inventor Chieh Hsieh

Chieh Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250246507
    Abstract: A semiconductor device includes a first interconnect structure, a device layer, a second interconnect structure, a diamond layer, a passivation layer, and an electrical connector. The device layer is disposed over the first interconnect structure. The second interconnect structure is disposed over the device layer and comprises a topmost metallization pattern. The diamond layer is disposed over the second interconnect structure and at least revealing a part of the topmost metallization pattern. The passivation layer covers the diamond layer and reveals the part of the topmost metallization pattern. The electrical connector is disposed over the passivation layer and bonded to the part of the topmost metallization pattern.
    Type: Application
    Filed: January 29, 2024
    Publication date: July 31, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Jong Chia, Yu-Jen Lien, Ke-Han Shen, Cheng-Chieh Hsieh, Kuo-Chung Yee, Szu-Wei Lu, Chung-Ju Lee, Chen-Hua Yu, Ji CUI, Chih-Ming Ke, Hung-Yi Kuo
  • Patent number: 12374627
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Grant
    Filed: June 6, 2024
    Date of Patent: July 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Patent number: 12362283
    Abstract: A semiconductor device includes a stacked structure, first conductive terminals and second conductive terminals. The stacked structure includes a first semiconductor component having a first area and a second semiconductor component stacked on the first semiconductor component and having a second area smaller than the first area, wherein an extending direction of the first area and an extending direction of the second area are perpendicular to a stacking direction of the first semiconductor component and the second semiconductor component. The first conductive terminals are located on the stacked structure, electrically coupled to the first semiconductor component and aside of the second semiconductor component. The second conductive terminals are located on the stacked structure and electrically coupled to the second semiconductor component.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: July 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hung Tseng, Cheng-Chieh Hsieh, Hao-Yi Tsai
  • Patent number: 12362329
    Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via.
    Type: Grant
    Filed: February 1, 2024
    Date of Patent: July 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
  • Patent number: 12359298
    Abstract: A manufacturing method of an antimicrobial and adhesion-proof titanium tableware having a contact portion for contacting foods, food ingredients, drinking water, beverages, or body parts of a user. The manufacturing method includes a preparation step implemented by using a titanium substrate to produce a tableware preform; a preparation step implemented by using a titanium substrate to produce a tableware preform; a surface treatment step implemented by washing a surface of the tableware preform and removing a primary oxidation layer on the surface of the tableware preform; and an oxidation step which includes: placing the tableware preform in a vacuum calcination furnace, heating the tableware preform to reach a temperature ranging from 700° C. to 850° C., and introducing oxygen for allowing one part of the surface of the tableware preform corresponding to the contact portion to be exposed to the oxygen for 3 hours to 12 hours.
    Type: Grant
    Filed: April 10, 2024
    Date of Patent: July 15, 2025
    Assignee: TIMAS TITAN CO., LTD.
    Inventors: Han-Chun Hsieh, Han-Chieh Hsieh
  • Patent number: 12360321
    Abstract: A semiconductor device includes an optical connector element and an optical coupler. The optical connector element includes a base structure, a first polymer via and a cladding layer. The base structure has a first surface and a second surface opposite to the first surface. The first polymer via passes through the base structure from the first surface to the second surface. The cladding layer is surrounding the first polymer via, wherein a refractive index of the cladding layer is different than a refractive index of the first polymer via. The optical coupler is disposed over the optical connector element, wherein the optical coupler receives optical signals from the first polymer via.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: July 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Yu-Hao Chen
  • Publication number: 20250218890
    Abstract: An integrated circuit package and the method of forming the same are provided. The integrated circuit package may comprise a substrate, a first package component bonded to the substrate and a first cooling system over the first package component. The first package component may comprise a first semiconductor die. The first cooling system may comprise a first base over the first package component, wherein the first base may comprise a first recess, a first pin protruding from a bottom of the first recess, and a first raised portion encircling the recess in a top-down view; a lid over the first base, wherein the lid may be spaced apart from the first pin; and a sealant connecting the lid to the first raised portion of the first base.
    Type: Application
    Filed: December 27, 2023
    Publication date: July 3, 2025
    Inventors: Yu-Jen Lien, Cheng-Chieh Hsieh, Chen-Hua Yu, Ke-Han Shen, Hung-Yi Kuo
  • Publication number: 20250192112
    Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via.
    Type: Application
    Filed: February 24, 2025
    Publication date: June 12, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
  • Patent number: 12315784
    Abstract: A semiconductor package and a manufacturing method thereof is provided. The semiconductor package includes a first semiconductor die, including a substrate and transistors formed at a front side of the substrate; a power distribution network, spreading at a back side of the substrate and penetrating through the substrate, to provide power and ground signals to the transistors; a dielectric material, laterally surrounding the first semiconductor die; and a second semiconductor die, having a central portion bonded with the first semiconductor die and a peripheral portion in contact with the dielectric material.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: May 27, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Yi Kuo, Cheng-Chieh Hsieh, Kuo-Chung Yee, Chen-Hua Yu
  • Publication number: 20250167075
    Abstract: Semiconductor devices and methods of manufacture are presented herein. In accordance with some embodiments, a device includes a first semiconductor device, the first semiconductor device including a first interconnect structure, an integrated cooling structure bonded to the first interconnect structure, wherein the integrated cooling structure is configured for a working fluid to enter and exit the integrated cooling structure, a second semiconductor device including a second interconnect structure, the second semiconductor device bonded to the integrated cooling structure opposite the first interconnect structure, and a plurality of through substrate vias extending through the integrated cooling structure, wherein the plurality of through substrate vias electrically couple the first semiconductor device to the second semiconductor device.
    Type: Application
    Filed: November 17, 2023
    Publication date: May 22, 2025
    Inventors: Yu-Jen Lien, Chen-Hua Yu, Cheng-Chieh Hsieh, Kuo-Chung Yee, Hung-Yi Kuo, Ke-Han Shen
  • Publication number: 20250151391
    Abstract: A semiconductor structure is provided. A logic cell with a logic function includes P-type and N-type transistors in first and second active regions over a semiconductor substrate, first and a second isolation structures on opposite edges of the first and second active regions, first and third transistors in the first and second active regions and between the first isolation structure and the P-type transistors, second and fourth transistors in the first and second active region and between the second isolation structure and the P-type transistors. Each of the N-type transistors and a respective P-type transistor shares a first gate electrode along the first direction. The first and third transistors share a second gate electrode extending along the first direction. The second and fourth transistors share a third gate electrode extending along the first direction. The P-type transistors and the N-type transistors are configured to perform the logic function.
    Type: Application
    Filed: January 3, 2025
    Publication date: May 8, 2025
    Inventors: Kin-Hooi DIA, Ho-Chieh HSIEH
  • Publication number: 20250147439
    Abstract: A method includes irradiating debris deposited in an extreme ultraviolet (EUV) lithography system with laser, controlling one or more of a wavelength of the laser or power of the laser to selectively vaporize the debris and limit damage to the EUV) lithography system, and removing the vaporized debris.
    Type: Application
    Filed: December 26, 2024
    Publication date: May 8, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Han LIN, Chieh HSIEH, Sheng-Kang YU, Shang-Chieh CHIEN, Heng-Hsin LIU, Li-Jui CHEN
  • Publication number: 20250123458
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Application
    Filed: December 18, 2024
    Publication date: April 17, 2025
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Publication number: 20250120043
    Abstract: An immersion cooling equipment is configured to cool an electronic device. The immersion cooling equipment includes a tank and a hollow fluid blocking member. The tank is filled with coolant. The electronic device is disposed in the tank and immersed in the coolant. The hollow fluid blocking member is replaceably placed in the tank to be immersed in the coolant. During a process of placing the hollow fluid blocking member into the tank, a portion of the coolant in the tank flows into the hollow fluid blocking member, and during a process of detaching the hollow fluid blocking member from the tank, the coolant in the hollow fluid blocking member flows out of the hollow fluid blocking member and flows back to the tank.
    Type: Application
    Filed: May 6, 2024
    Publication date: April 10, 2025
    Applicant: Wiwynn Corporation
    Inventors: You-Cheng Wang, Kang-Bin Mah, Tzu-Hsuan Feng, Hsien-Chieh Hsieh
  • Patent number: 12266639
    Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
  • Publication number: 20250104891
    Abstract: An immersion cooling system includes a cooling tank, a busbar and a feedthrough module. The cooling tank includes a side wall and an opening formed on the side wall. The busbar is disposed in the cooling tank. The feedthrough module seals the opening. The feedthrough module includes a base, a conductive member, an insulating member and an electrical connector. The base is disposed on the side wall. The base has a through hole corresponding to the opening. The insulating member is disposed between the conductive member and the base to insulate the conductive member from the base. The electrical connector is connected to the conductive member. The electrical connector passes through the through hole and the opening to be connected to the busbar.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Applicant: Wiwynn Corporation
    Inventors: Hsien-Chieh Hsieh, Ting-Ya Liao
  • Publication number: 20250070013
    Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.
    Type: Application
    Filed: November 14, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
  • Patent number: 12235594
    Abstract: A method for performing a lithography process is provided. The method includes forming a photoresist layer over a substrate, providing a plurality of target droplets to a source vessel, and providing a plurality of first laser pulses according to a control signal provided by a controller to irradiate the target droplets in the source vessel to generate plasma as an EUV radiation. The plasma is generated when the control signal indicates a temperature of the source vessel is within a temperature threshold value. The method further includes directing the EUV radiation from the source vessel to the photoresist layer to form a patterned photoresist layer and developing and etching the patterned photoresist layer to form a circuit layout.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi Yang, Ssu-Yu Chen, Shang-Chieh Chien, Chieh Hsieh, Tzung-Chi Fu, Bo-Tsun Liu, Li-Jui Chen, Po-Chung Cheng
  • Publication number: 20250060542
    Abstract: A package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. The prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.
    Type: Application
    Filed: November 3, 2024
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Hsiang Hsu, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Chung-Ming Weng
  • Patent number: 12222404
    Abstract: A current load circuit for testing a power supply circuit includes a control circuit and a load generation circuit. The control circuit is configured to generate a reset signal according to a clock signal. The load generation circuit is coupled to the control circuit and has several load configurations. The load generation circuit is configured to provide one of the load configurations as a current load of the load generation circuit according to the clock signal and the reset signal and receive a portion of the supply current provided by the power supply circuit according to the current load to generate an indication signal for indicating a performance of the power supply circuit.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: February 11, 2025
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Han-Chieh Hsieh