Patents by Inventor Chieh Hsieh

Chieh Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11646738
    Abstract: The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: May 9, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chao-Min Lai, Han-Chieh Hsieh, Tang-Hung Chang, Hung-Wei Wang, Chun-Yi Kuo
  • Patent number: 11647578
    Abstract: A light source is provided capable of maintaining the temperature of a collector surface at or below a predetermined temperature. The light source in accordance with various embodiments of the present disclosure includes a processor, a droplet generator for generating a droplet to create extreme ultraviolet light, a collector for reflecting the extreme ultraviolet light into an intermediate focus point, a light generator for generating pre-pulse light and main pulse light, and a thermal image capture device for capturing a thermal image from a reflective surface of the collector.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: May 9, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yu Chen, Cho-Ying Lin, Sagar Deepak Khivsara, Hsiang Chen, Chieh Hsieh, Sheng-Kang Yu, Shang-Chieh Chien, Kai Tak Lam, Li-Jui Chen, Heng-Hsin Liu, Zhiqiang Wu
  • Patent number: 11640935
    Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: May 2, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
  • Patent number: 11635566
    Abstract: An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan Tai, Chung-Ming Weng, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11633067
    Abstract: A metal cutting board is integrally formed by a metal plate body and includes a first plate body, a second plate body, and an inclined connecting portion. The second plate body is disposed around a periphery of the first plate body, the second plate body and the first plate body are parallel to each other, and the second plate body and the first plate body are positioned on planes of different heights. The inclined connecting portion is circumferentially disposed between the first plate body and the second plate body. The first plate body, the second plate body, and the inclined connecting portion are integrally formed from the metal plate body and are connected to form a shallow tray structure.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: April 25, 2023
    Assignee: TIMAS TITAN CO., LTD.
    Inventors: Han-Chun Hsieh, Han-Chieh Hsieh
  • Publication number: 20230123871
    Abstract: An antimicrobial and adhesion-proof titanium tableware and a manufacturing method of the same are provided. The antimicrobial and adhesion-proof titanium tableware is made of a titanium substrate, and includes a contact portion and an oxidation layer structure. The contact portion is used for contacting foods, food ingredients, drinking water, beverages, or body parts of a user. The oxidation layer structure is formed on one part of a surface of the titanium substrate corresponding to the contact portion. The titanium substrate is made of titanium in ? phase, and the oxidation layer structure is a titanium dioxide film in a rutile crystalline form. The oxidation layer structure has a roughened surface and an oxygen diffusion layer formed at an interface of the oxidation layer structure and the titanium substrate.
    Type: Application
    Filed: September 19, 2022
    Publication date: April 20, 2023
    Inventors: Han-Chun Hsieh, Han-Chieh Hsieh
  • Patent number: 11630393
    Abstract: An apparatus for generating extreme ultraviolet (EUV) radiation includes a droplet generator configured to generate target droplets. An excitation laser is configured to heat the target droplets using excitation pulses to convert the target droplets to plasma. An energy detector is configured to measure a variation in EUV energy generated when the target droplets are converted to plasma. A feedback controller is configured to adjust parameters of the droplet generator and/or the excitation laser based on the variation in EUV energy.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh Hsieh, Kuan-Hung Chen, Chun-Chia Hsu, Shang-Chieh Chien, Bo-Tsun Liu, Li-Jui Chen, Po-Chung Cheng
  • Patent number: 11632849
    Abstract: A shutter is provided near the immediate focus of a lithography apparatus in order to deflect tin debris generated by a source side of the apparatus away from a scanner side of the apparatus and towards a debris collection device. The activation of the shutter is synchronized with the generation of light pulses so as not to block light from entering the scanner side.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh Hsieh, Tai-Yu Chen, Hung-Jung Hsu, Cho-Ying Lin, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Publication number: 20230112750
    Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 13, 2023
    Inventors: Chang-Chia Huang, Tsung-Shu Lin, Cheng-Chieh Hsieh, Wei-Cheng Wu
  • Patent number: 11614592
    Abstract: Photonic devices and methods of manufacture are provided. In embodiments a fill material and/or a secondary waveguide are utilized in order to protect other internal structures such as grating couplers from the rigors of subsequent processing steps. Through the use of these structures at the appropriate times during the manufacturing process, damage and debris that would otherwise interfere with the manufacturing process of the device or operation of the device can be avoided.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Chih-Hsuan Tai, Hua-Kuei Lin, Tsung-Yuan Yu, Min-Hsiang Hsu
  • Publication number: 20230064840
    Abstract: A shutter is provided near the immediate focus of a lithography apparatus in order to deflect tin debris generated by a source side of the apparatus away from a scanner side of the apparatus and towards a debris collection device. The activation of the shutter is synchronized with the generation of light pulses so as not to block light from entering the scanner side.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Chieh HSIEH, Tai-Yu CHEN, Hung-Jung HSU, Cho-Ying LIN, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
  • Publication number: 20230065403
    Abstract: A light source is provided capable of maintaining the temperature of a collector surface at or below a predetermined temperature. The light source in accordance with various embodiments of the present disclosure includes a processor, a droplet generator for generating a droplet to create extreme ultraviolet light, a collector for reflecting the extreme ultraviolet light into an intermediate focus point, a light generator for generating pre-pulse light and main pulse light, and a thermal image capture device for capturing a thermal image from a reflective surface of the collector.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Tai-Yu CHEN, Cho-Ying LIN, Sagar Deepak KHIVSARA, Hsiang CHEN, Chieh HSIEH, Sheng-Kang YU, Shang-Chieh CHIEN, Kai Tak LAM, Li-Jui CHEN, Heng-Hsin LIU, Zhiqiang WU
  • Publication number: 20230060899
    Abstract: A lithography system is provided capable of deterring contaminants, such as tin debris from entering into the scanner. The lithography system in accordance with various embodiments of the present disclosure includes a processor, an extreme ultraviolet light source, a scanner, and a hollow connection member. The light source includes a droplet generator for generating a droplet, a collector for reflecting extreme ultraviolet light into an intermediate focus point, and a light generator for generating pre-pulse light and main pulse light. The droplet generates the extreme ultraviolet light in response to the droplet being illuminated with the pre-pulse light and the main pulse light. The scanner includes a wafer stage. The hollow connection member includes an inlet that is in fluid communication with an exhaust pump. The hollow connection member provides a hollow space in which the intermediate focus point is disposed.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Chieh HSIEH, Tai-Yu CHEN, Cho-Ying LIN, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
  • Publication number: 20230060720
    Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
  • Publication number: 20230062653
    Abstract: Supersonic gas jets are provided near the immediate focus of a lithography apparatus in order to deflect tin debris generated by the lithography process away from a scanner side and towards a debris collection device. The gas jets can be positioned in a variety of useful orientations, with adjustable gas flow velocity and gas density in order to prevent up to nearly 100% of the tin debris from migrating to the reticle on the scanner side.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Chih-Ping YEN, Yen-Shuo SU, Chieh HSIEH, Shang-Chieh CHIEN, Chun-Lin CHANG, Li-Jui CHEN, Heng-Hsin LIU
  • Publication number: 20230066363
    Abstract: A package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. The prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Hsiang Hsu, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Chung-Ming Weng
  • Publication number: 20230060855
    Abstract: A processor circuit includes a processor, N detection circuits and a neural network circuit. The processor is configured to provide a control signal. The control signal indicates an operational status of the processor. The N detection circuits are configured to detect N different types of variation factors affecting an operating voltage of the processor respectively, and accordingly generate N detection results respectively. N is an integer greater than one. The neural network circuit, coupled to the processor and the N detection circuits, is configured to determine the operating voltage of the processor according to the control signal and the N detection results.
    Type: Application
    Filed: June 15, 2022
    Publication date: March 2, 2023
    Inventor: HAN-CHIEH HSIEH
  • Publication number: 20230065941
    Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, an insulating encapsulation, and a plurality of conductive pillars. The second semiconductor die is located on and electrically communicates to the first semiconductor die through joints therebetween. The insulating encapsulation encapsulates the first semiconductor die and the second semiconductor die and covers the joints. The plurality of conductive pillars is next to and electrically connected to the first semiconductor die and the second semiconductor die, and is covered by the insulating encapsulation.
    Type: Application
    Filed: August 29, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Tzuan-Horng Liu, Cheng-Chieh Hsieh, Tsung-Yuan Yu
  • Patent number: 11592466
    Abstract: A probe card device and a self-aligned probe are provided. The self-aligned probe includes a fixing end portion configured to be abutted against a space transformer, a testing end portion configured to detachably abut against a device under test (DUT), a first connection portion connected to the fixing end portion, a second connection portion connected to the testing end portion, and an arced portion that connects the first connection portion and the second connection portion. The fixing end portion and the testing end portion jointly define a reference line passing there-through. The first connection portion has an aligned protrusion, and a maximum distance between the arced portion and the reference line is greater than 75 ?m and is less than 150 ?m.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: February 28, 2023
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Kai-Chieh Hsieh, Wei-Jhih Su, Hong-Ming Chen, Vel Sankar Ramachandran
  • Patent number: 11594520
    Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Cheng-Chieh Hsieh, Ming-Yen Chiu