Patents by Inventor Chieh Hsieh

Chieh Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12055867
    Abstract: A lithography system is provided capable of deterring contaminants, such as tin debris from entering into the scanner. The lithography system in accordance with various embodiments of the present disclosure includes a processor, an extreme ultraviolet light source, a scanner, and a hollow connection member. The light source includes a droplet generator for generating a droplet, a collector for reflecting extreme ultraviolet light into an intermediate focus point, and a light generator for generating pre-pulse light and main pulse light. The droplet generates the extreme ultraviolet light in response to the droplet being illuminated with the pre-pulse light and the main pulse light. The scanner includes a wafer stage. The hollow connection member includes an inlet that is in fluid communication with an exhaust pump. The hollow connection member provides a hollow space in which the intermediate focus point is disposed.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: August 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chieh Hsieh, Tai-Yu Chen, Cho-Ying Lin, Heng-Hsin Liu, Li-Jui Chen, Shang-Chieh Chien
  • Publication number: 20240254614
    Abstract: A manufacturing method of an antimicrobial and adhesion-proof titanium tableware having a contact portion for contacting foods, food ingredients, drinking water, beverages, or body parts of a user. The manufacturing method includes a preparation step implemented by using a titanium substrate to produce a tableware preform; a preparation step implemented by using a titanium substrate to produce a tableware preform; a surface treatment step implemented by washing a surface of the tableware preform and removing a primary oxidation layer on the surface of the tableware preform; and an oxidation step which includes: placing the tableware preform in a vacuum calcination furnace, heating the tableware preform to reach a temperature ranging from 700° C. to 850° C., and introducing oxygen for allowing one part of the surface of the tableware preform corresponding to the contact portion to be exposed to the oxygen for 3 hours to 12 hours.
    Type: Application
    Filed: April 10, 2024
    Publication date: August 1, 2024
    Inventors: Han-Chun Hsieh, Han-Chieh Hsieh
  • Patent number: 12046543
    Abstract: A package substrate and a chip package structure using the same are provided. The package substrate includes a laminated board including first to third wiring layers, a pad array, a plurality of ground conductive structures, and a plurality of power conductive structures. At least one of the ground (or power) conductive structures includes two first ground (or power) conductive posts and a second ground (or power) conductive post. The two first ground (or power) conductive posts and the second ground (or power) conductive post are arranged along a first direction, and the second ground (or power) conductive post is located between two orthographic projections of the two first ground (or power) conductive posts. Each of the ground conductive structures in a first column and each of the power conductive structures in a second column are offset from each other in a second direction.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: July 23, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Han-Chieh Hsieh, Chao-Min Lai, Cheng-Chen Huang, Nan-Chin Chuang
  • Patent number: 12044975
    Abstract: A method of controlling a droplet illumination module/droplet detection module system of an extreme ultraviolet (EUV) radiation source includes irradiating a target droplet with light from a droplet illumination module and detecting light reflected and/or scattered by the target droplet. The method includes determining whether an intensity of the detected light is within an acceptable range. In response to determining that the intensity of the detected light is not within the acceptable range, a parameter of the droplet illumination module is automatically adjusted to set the intensity of the detected light within the acceptable range.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jen-Yang Chung, Chieh Hsieh, Shang-Chieh Chien, Li-Jui Chen, Po-Chung Cheng
  • Publication number: 20240240871
    Abstract: An immersion cooling system includes a work tank, a pump, a first pipeline, a condensation dehumidification device, a second pipeline, and a control system. The work tank includes a vapor section and a humidity sensor for sensing a humidity of the vapor section. The first pipeline includes a first valve. The vapor section and the pump are selectively in communication with each other or not when the first valve is actuated. The condensation dehumidification device has a first end and a second end, where the first end is in communication with the pump. The second pipeline includes a second valve. The condensation dehumidification device and the tank are selectively in communication with each other or not when the second valve is actuated. When the humidity is greater than a preset humidity, the control system controls the first valve to communicate the vapor section and the pump and activates the pump.
    Type: Application
    Filed: December 4, 2023
    Publication date: July 18, 2024
    Inventors: Hsien-Chieh Hsieh, Tsung-Han Li
  • Patent number: 12035826
    Abstract: A beverage container assembly and a cover component thereof are provided. The beverage container assembly includes a beverage container, the cover component, and a straw. The cover component includes a first cover and a second cover pivotally connected thereto. The first cover has a top portion that includes an opening portion and a pivot portion, and has a sleeve portion that is connected to a lower end of the top portion. The second cover has a connecting arm and a main body portion that has a straw accommodating portion. A pivot end of the connecting arm has two first pivots that protrude outward and an expansion joint located at a center of the pivot end, so that a distance between terminal ends of the two first pivots can be shortened for easy engagement with or separation from two first pivot holes on the pivot portion.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: July 16, 2024
    Assignee: TIMAS TITAN CO., LTD.
    Inventors: Han-Chun Hsieh, Han-Chieh Hsieh
  • Patent number: 12040283
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Publication number: 20240234375
    Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via.
    Type: Application
    Filed: February 1, 2024
    Publication date: July 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
  • Publication number: 20240224468
    Abstract: A delivery device includes a first base, two first check valves, a carrier, a first deformable container and a driving mechanism. The first base has a first inlet and a first outlet. The two first check valves are disposed at the first inlet and the first outlet. The first deformable container is connected to the first base and the carrier. The first deformable container communicates with the first inlet and the first outlet. The driving mechanism is connected to the carrier. The driving mechanism drives the carrier to reciprocate, such that the carrier drives the first deformable container to expand or contract.
    Type: Application
    Filed: April 20, 2023
    Publication date: July 4, 2024
    Applicant: Wiwynn Corporation
    Inventor: Hsien-Chieh Hsieh
  • Publication number: 20240210636
    Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
    Type: Application
    Filed: March 5, 2024
    Publication date: June 27, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 12019378
    Abstract: A method includes: removing debris on a collector of a lithography equipment by changing physical structure of the debris with a cleaner, the cleaner being at a temperature less than about 13 degrees Celsius; forming a cleaned collector by exhausting the removable debris from the collector; and forming openings in a mask layer on a substrate by removing regions of the mask layer exposed to radiation from the cleaned collector.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: June 25, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cho-Ying Lin, Tai-Yu Chen, Chieh Hsieh, Sheng-Kang Yu, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Publication number: 20240203317
    Abstract: An electronic device includes a display panel, a gate driving circuit and a control unit. The display panel includes a display scan line and a dummy scan line. The gate driving circuit includes a first output unit for providing a display scan signal to the display scan line, and a second output unit for providing a test scan signal to the dummy scan line. The control unit is electrically connected to the gate driving circuit for receiving the test scan signal, updating a driving voltage according to the test scan signal, and driving the gate driving circuit according to the updated driving voltage.
    Type: Application
    Filed: November 15, 2023
    Publication date: June 20, 2024
    Applicant: InnoLux Corporation
    Inventors: Yu-Hsin FENG, Yu-Tse Lu, Jen-Chieh HSIEH, Yao-Lien HSIEH
  • Publication number: 20240192456
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Application
    Filed: February 26, 2024
    Publication date: June 13, 2024
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 12002799
    Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Hung-Yi Kuo, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Yuan Yu, Ming Hung Tseng
  • Patent number: 11993853
    Abstract: An antimicrobial and adhesion-proof titanium tableware and a manufacturing method of the same are provided. The antimicrobial and adhesion-proof titanium tableware is made of a titanium substrate, and includes a contact portion and an oxidation layer structure. The contact portion is used for contacting foods, food ingredients, drinking water, beverages, or body parts of a user. The oxidation layer structure is formed on one part of a surface of the titanium substrate corresponding to the contact portion. The titanium substrate is made of titanium in ? phase, and the oxidation layer structure is a titanium dioxide film in a rutile crystalline form. The oxidation layer structure has a roughened surface and an oxygen diffusion layer formed at an interface of the oxidation layer structure and the titanium substrate.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: May 28, 2024
    Assignee: TIMAS TITAN CO., LTD.
    Inventors: Han-Chun Hsieh, Han-Chieh Hsieh
  • Patent number: 11986792
    Abstract: The present invention provides a photocuring device, comprising a housing and an ultraviolet (UV) light module, wherein the housing comprises an electroluminescent layer and/or a touch layer and a control module connected to the electroluminescent layer and/or the touch layer by an electrical means. The photocuring device of the invention not only features a low material cost and low production cost, but also allows its display interface and/or operation interface to be provided at any position of the housing of the photocuring device, without limitations in size, shape, or angle. Furthermore, the photocuring device of the invention allows its display interface and/or operation interface to be simplified as needed to facilitate operation and viewing by a manicurist or one who is receiving a manicure.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: May 21, 2024
    Assignee: COSMEX CO., LTD.
    Inventors: Wan-Chieh Hsieh, Ya-Wen Wu, Yu-Ching Li, Wen-Shan Chung
  • Publication number: 20240146205
    Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.
    Type: Application
    Filed: September 23, 2023
    Publication date: May 2, 2024
    Inventors: Shin-Li Lin, He-Yi Shu, Shih-Jen Yang, Ta-Yung Yang, Yi-Min Shiu, Chih-Ching Lee, Yu-Chieh Hsieh, Chao-Chi Chen
  • Patent number: 11964881
    Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 23, 2024
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
  • Publication number: 20240128149
    Abstract: Some implementations described herein include systems and techniques for fabricating a semiconductor die package that includes a cooling interface region formed in surface of an integrated circuit die. The cooling interface region, which includes a combination of channel regions and pillar structures, may be directly exposed to a fluid above and/or around the semiconductor die package.
    Type: Application
    Filed: March 27, 2023
    Publication date: April 18, 2024
    Inventors: Cheng-Chieh HSIEH, Wei-Kong SHENG, Ke-Han SHEN, Yu-Jen LIEN
  • Patent number: 11953740
    Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu