Patents by Inventor Chieh Hsieh
Chieh Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12222545Abstract: An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.Type: GrantFiled: April 18, 2023Date of Patent: February 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hsuan Tai, Chung-Ming Weng, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 12216413Abstract: A method includes irradiating debris deposited in an extreme ultraviolet (EUV) lithography system with laser, controlling one or more of a wavelength of the laser or power of the laser to selectively vaporize the debris and limit damage to the EUV) lithography system, and removing the vaporized debris.Type: GrantFiled: August 7, 2023Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Han Lin, Chieh Hsieh, Sheng-Kang Yu, Shang-Chieh Chien, Heng-Hsin Liu, Li-Jui Chen
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Publication number: 20250038133Abstract: A semiconductor structure and a semiconductor die are provided. The semiconductor structure includes a semiconductor substrate, an electronic circuit, a first seal ring, a buffer zone and a conductive routing. The semiconductor substrate has a circuit region and a seal ring region surrounding the circuit region. The electronic circuit is disposed on the semiconductor substrate in the circuit region. The first seal ring is disposed on the semiconductor substrate in the seal ring region and surrounding the circuit region. The buffer zone is located in the seal ring region and interposed between the circuit region and the first seal ring. The first seal ring is separated from the circuit region by the buffer zone. The conductive routing is disposed on the semiconductor substrate in the buffer zone. The conductive routing is electrically connected to the electronic circuit.Type: ApplicationFiled: June 26, 2024Publication date: January 30, 2025Inventors: Chi-Shun CHENG, Yung-Chieh YU, Yi-Chieh HSIEH
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Publication number: 20250038073Abstract: A package structure and a method for forming the same are provided. The package structure includes a first package structure and a second package structure. The first package structure includes a first device formed over a first substrate. The first device includes a first conductive plug connected to a through substrate via (TSV) structure formed in the first substrate. A buffer layer surrounds the first substrate. A first bonding layer is formed over the first substrate and the buffer layer. The second package structure includes a second device formed over a second substrate. A second bonding layer is formed over the second device. A hybrid bonding structure is between the first package structure and the second package structure by bonding the first bonding layer to the second bonding layer.Type: ApplicationFiled: July 27, 2023Publication date: January 30, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Han SHEN, Chih-Yuan CHEN, Jiung WU, Hung-Yi Kuo, Chung-Ju LEE, Tung-He CHOU, Ji CUI, Kuo-Chung YEE, Chen-Hua YU, Cheng-Chieh HSIEH, Yu-Jen LIEN, Yian-Liang KUO, Shih-Hao TSENG, Jen Yu WANG, Tzu-Chieh Chou
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Patent number: 12210188Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.Type: GrantFiled: August 29, 2022Date of Patent: January 28, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Kuo, Chen-Hua Yu, Cheng-Chieh Hsieh, Che-Hsiang Hsu, Chung-Ming Weng, Tsung-Yuan Yu
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Patent number: 12210200Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: GrantFiled: February 26, 2024Date of Patent: January 28, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 12191310Abstract: A semiconductor structure is provided. A logic cell with a logic function includes a plurality of first transistors in an active region over a semiconductor substrate, a second transistor in the active region, a third transistor in the active region, and first and second isolation structures on opposite edges of the active region and extending along the first direction. Each first transistor includes a first gate electrode extending along the first direction. The second transistor includes a second gate electrode extending along the first direction. The third transistor includes a third gate electrode extending along the first direction. The first gate electrodes are disposed between the first and second isolation structures. The second gate electrode is disposed between the first gate electrodes and the first isolation structure. The third gate electrode is disposed between the first gate electrodes and the second isolation structure.Type: GrantFiled: November 26, 2021Date of Patent: January 7, 2025Assignee: MEDIATEK INC.Inventors: Kin-Hooi Dia, Ho-Chieh Hsieh
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Publication number: 20250005256Abstract: The present invention provides a method for placing and routing a circuit design on an integrated circuit. The method includes the steps of: placing a plurality of standard cells in the circuit design; searching for the standard cells with power-to-power abutment in the circuit design; and performing an operation on the standard cells with the power-to-power abutment for a power/performance/area optimization.Type: ApplicationFiled: June 4, 2024Publication date: January 2, 2025Applicant: MEDIATEK INC.Inventors: Ho-Chieh Hsieh, Kin-Hooi Dia
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Patent number: 12183257Abstract: An electronic device includes a display panel, a gate driving circuit and a control unit. The display panel includes a display scan line and a dummy scan line. The gate driving circuit includes a first output unit for providing a display scan signal to the display scan line, and a second output unit for providing a test scan signal to the dummy scan line. The control unit is electrically connected to the gate driving circuit for receiving the test scan signal, updating a driving voltage according to the test scan signal, and driving the gate driving circuit according to the updated driving voltage.Type: GrantFiled: November 15, 2023Date of Patent: December 31, 2024Assignee: InnoLux CorporationInventors: Yu-Hsin Feng, Yu-Tse Lu, Jen-Chieh Hsieh, Yao-Lien Hsieh
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Patent number: 12176282Abstract: A manufacturing method of a semiconductor package includes the following steps. A supporting layer is formed over a redistribution structure. A first planarization process is performed over the supporting layer. A lower dielectric layer is formed over the supporting layer, wherein the lower dielectric layer includes a concave exposing a device mounting region of the supporting layer. A first sacrificial layer is formed over the supporting layer, wherein the sacrificial layer filling the concave. A second planarization process is performed over the lower dielectric layer and the first sacrificial layer. A transition waveguide provided over the lower dielectric layer. The first sacrificial layer is removed. A semiconductor device is mounted over the device mounting region, wherein the semiconductor device includes a device waveguide is optically coupled to the transition waveguide.Type: GrantFiled: March 27, 2023Date of Patent: December 24, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
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Patent number: 12174545Abstract: A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become a plasma and emit extreme ultraviolet radiation. The photolithography system senses contamination of a collector mirror by the tin droplets and adjusts the flow of a buffer fluid to reduce the contamination.Type: GrantFiled: July 28, 2023Date of Patent: December 24, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yu Chen, Sagar Deepak Khivsara, Kuo-An Liu, Chieh Hsieh, Shang-Chieh Chien, Gwan-Sin Chang, Kai Tak Lam, Li-Jui Chen, Heng-Hsin Liu, Chung-Wei Wu, Zhiqiang Wu
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Publication number: 20240409280Abstract: A drink container and a lid assembly thereof are provided. The drink container includes a container body and the lid assembly, the lid assembly includes a first lid and a second lid, the first lid is screwed at an opening end of the container body through screw threads, the first lid has a top portion, and the top portion of the first lid has an opening portion. The second lid is disposed above the first lid, the second lid includes a plunger component, and a bottom portion of the plunger can be engaged with the opening portion and sealed with the opening portion. The plunger component is connected to a connection arm, and one side of the connection arm corresponding to the plunger component is pivotally connected to a pivot portion of the first lid. The plunger component has a second accommodating space configured to accommodate a straw.Type: ApplicationFiled: August 21, 2024Publication date: December 12, 2024Inventors: Han-Chun Hsieh, Han-Chieh Hsieh
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Publication number: 20240407578Abstract: A straw structure is provided. The straw structure includes a straw body, and the straw body has a first beveled edge at an opening of a bottom end of the straw body and a second beveled edge connected to a rear side of the first beveled edge. A puncturing end opening is formed at the first beveled edge and a side edge of the straw body, and the bottom end of the straw body has a beveled opening formed at the second beveled edge. The puncturing end opening is an acute angle that is less than 90 degrees, and a slope of the second beveled edge is greater than a slope of the first beveled edge.Type: ApplicationFiled: August 18, 2024Publication date: December 12, 2024Inventors: Han-Chun Hsieh, Han-Chieh Hsieh
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Patent number: 12164158Abstract: A package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. The prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.Type: GrantFiled: August 31, 2021Date of Patent: December 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Hsiang Hsu, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Chung-Ming Weng
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Publication number: 20240405005Abstract: A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package.Type: ApplicationFiled: July 25, 2024Publication date: December 5, 2024Inventors: Yu-Chia Lai, Cheng-Chieh Hsieh, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20240398159Abstract: An anti-stick titanium cookware and a method of manufacturing the same are provided. The anti-stick titanium cookware includes a titanium cookware body, a titanium cladding element, a heat-conducting element and an anti-stick layer. The titanium cookware body and the titanium cladding element are made of plate bodies, the titanium cladding element is welded on the lower surface of the titanium cookware body, and an interlayer space is formed between the titanium cladding element and the titanium cookware body. The heat-conducting element is accommodated in the interlayer space and contacts the lower surface of the titanium cookware body. The anti-stick layer is formed on the upper surface of the titanium cookware body. The heat-conducting element is fixed on the lower surface of the titanium cookware body through the titanium cladding element. The anti-stick layer is a titanium oxide film formed on the upper surface of the titanium cookware body.Type: ApplicationFiled: August 14, 2024Publication date: December 5, 2024Inventors: Han-Chun Hsieh, Han-Chieh Hsieh
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Publication number: 20240395756Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, an insulating encapsulation, and a plurality of conductive pillars. The second semiconductor die is located on and electrically communicates to the first semiconductor die through joints therebetween. The insulating encapsulation encapsulates the first semiconductor die and the second semiconductor die and covers the joints. The plurality of conductive pillars is next to and electrically connected to the first semiconductor die and the second semiconductor die, and is covered by the insulating encapsulation.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Tzuan-Horng Liu, Cheng-Chieh Hsieh, Tsung-Yuan Yu
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Publication number: 20240389215Abstract: A light source is provided capable of maintaining the temperature of a collector surface at or below a predetermined temperature. The light source in accordance with various embodiments of the present disclosure includes a processor, a droplet generator for generating a droplet to create extreme ultraviolet light, a collector for reflecting the extreme ultraviolet light into an intermediate focus point, a light generator for generating pre-pulse light and main pulse light, and a thermal image capture device for capturing a thermal image from a reflective surface of the collector.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Tai-Yu Chen, Cho-Ying Lin, Sagar Deepak Khivsara, Hsiang Chen, Chieh Hsieh, Sheng-Kang Yu, Shang-Chieh Chien, Kai Tak Lam, Li-Jui Chen, Heng-Hsin Liu, Zhiqiang Wu
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Publication number: 20240385370Abstract: An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Chih-Hsuan Tai, Chung-Ming Weng, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20240381570Abstract: An immersion cooling system includes a cooling tank, a busbar and two busbar protection modules. The busbar is disposed in the cooling tank. The two busbar protection modules are disposed at opposite sides of the busbar. Each of the two busbar protection modules includes a base, a driving member and a cover. The driving member is pivotally connected to the base. The cover is pivotally connected to the driving member. Two covers of the two busbar protection modules extend toward each other to cover the busbar. When two driving members of the two busbar protection modules are pushed, the two driving members rotate to drive the two covers to move away from each other, such that the busbar is exposed between the two covers.Type: ApplicationFiled: August 10, 2023Publication date: November 14, 2024Applicant: Wiwynn CorporationInventors: Ching-Wen Hsiao, Yun-Ya Chiu, Hsien-Chieh Hsieh