Abstract: Apparatuses and methods of operating the same are described. An apparatus including a display, an input device, and a processing device coupled to the display and the input device. The processing device may send an output to the display. The output may include a graphical object associated with a first step of a user-implemented procedure. The processing device may receive an input from the input device. The input may indicate a progress on an execution of the first step by an operator. The processing device may determine whether the input indicates that the operator has completed the first step. The processing device may determine whether the first step is a final step in the user-implemented procedure. The processing device may identify a second step in the user-implemented procedure when the input indicates that the operator has completed the first step and the first step is not a final step.

Abstract: Embodiments of the disclosure relate to methods for reducing or eliminating the first wafer effect after chamber cleans for plasma etch processes. In some embodiments, the wafer support is maintained at an elevated temperature relative to the etch process. In some embodiments, the etch process is a NF3+NH3 plasma etch to remove native oxides from a silicon substrate.

Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.

Abstract: The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

Abstract: An electronic device having a first area and a second area adjacent to the first area is provided, which includes a flexible substrate, a first conductive layer disposed on the flexible substrate and in the first area and the second area, a semiconductor disposed on the flexible substrate and electrically connected to the first conductive layer, a second conductive layer disposed on the first conductive layer, and an organic layer disposed on the first conductive layer and in the first area and the second area. The second conductive layer has a first portion and a second portion are respectively contacted the first conductive layer in the first area. In a cross-sectional view, a first portion of the organic layer is directly contacted the first conductive layer and the second conductive layer and disposed between the first portion and the second portion of the second conductive layer.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Abstract: A capillary refill time determining system is configured to judge a color variation of an image, and the capillary refill time determining system includes an electronic device including an image capturing unit, a storage unit and a processor. The storage unit is configured to access a refill start time and a default value. The processor is electronically connected to the image capturing unit and the storage unit, and the processor is configured to analyze an average color value of the image at an initial period, wherein at least one refill color value is obtained by analyzing the image according to the refill start time, the difference between the average color value and the refill color value is confirmed whether less than or equal to the default value, and a refill period is calculated between the refill start time and the refill end time.

Abstract: A multi-core processor includes a plurality of cores and a central dynamic voltage and frequency scaling (DVFS) system coupled to the plurality of core. The DVFS system is configured to receive power parameters and performance parameters for the plurality of cores. The power parameters may indicate power indices each respective core and the performance parameters may indicate performance for each respective core. The DVFS system may determine a power margin based on a target power budget for the multi-core processor and the power indices for the plurality of cores. For one or more cores of the plurality of cores, the DVFS system may dynamically allocate power to the core by determining an adjusted power index based on the power margin and the performance of the core. Accordingly, the DVFS system may dynamically balance performance and power of the cores.

Abstract: This invention discloses an etching solution and a manufacturing method of a display panel. The method includes following steps: providing a substrate; forming a conductive layer stack including a first sub-layer, a second sub-layer and a third sub-layer on the substrate, the first sub-layer includes molybdenum, the second sub-layer is disposed on the first sub-layer and includes a transparent conductive material including indium-containing oxide, the third sub-layer is disposed between the first sub-layer and the second sub-layer and includes silver or silver alloy; performing an etching process, the first sub-layer, the second sub-layer and the third sub-layer are etched by an etching solution to form a first patterned sub-layer, a second patterned sub-layer and a third patterned sub-layer. The etching solution includes 1 to 3 wt % of nitric acid, 30 to 50 wt % of acetic acid, 30 to 50 wt % of phosphoric acid and a remaining amount of water.

Abstract: A method for manufacturing an electronic device and a transferring head are provided. The method includes providing a plurality of microcomponents on a first substrate; providing a transferring head, wherein the transferring head includes a substrate and a head unit disposed on a side of the substrate, the head unit includes a layer, and the layer has a first portion and a second portion, wherein a thickness of the first portion is greater than a thickness of the second portion, and a difference between the thickness of the first portion and the thickness of the second portion is greater than or equal to 20 ?m and less than or equal to 70 ?m; contacting at least one microcomponent by a picking surface of the first portion; and transferring the microcomponent from the first substrate to a second substrate by the transferring head.

Abstract: A dual-band transform circuit structure includes a first transmission line, a second transmission line, and a conductive layer. The first transmission line has a first input terminal, a first output terminal, and a second output terminal. The second transmission line has a second input terminal, a third input terminal, a third output terminal, and a fourth output terminal. The second input terminal is coupled to the first output terminal, and the third input terminal is coupled to the second output terminal. The conductive layer is stacked with the first transmission and the second transmission line. The conductive layer includes a first hollow pattern. The first hollow pattern and the second transmission line are overlapped in a top view.

Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

Abstract: The present disclosure provides a decellularized extracellular matrix, the preparation process and uses thereof. The decellularized extracellular matrix of the present disclosure is derived from a three-dimensional cell spheroid, and the decellularized extracellular matrix has a three-dimensional spherical structure. The decellularized extracellular matrix of the present disclosure can be used to prepare a biomedical material scaffold for promoting tissue regeneration and repair.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.

Abstract: This disclosure provides antibodies and antigen-binding fragments that can be administered to a subject that has been bitten by a venomous snake. Antibodies and antigen-binding fragments herein can be capable of treating or curing the subject and may provide protection against snake venom for up to several weeks. A combination or population of antibodies and antigen-binding fragments can be administered to the subject where the type of snake is not known or where a subject has been bitten by more than one species of snake. This disclosure further provides methods for identification of such broadly-neutralizing antibodies.

Abstract: The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.

Abstract: A transceiver system includes a signal generator and controller circuit, a first signal converter circuit, an attenuator circuit, and a second signal converter circuit. Signal generator and controller circuit generates a transmitting baseband signal. First signal converter circuit generates a transmitting radio frequency signal according to transmitting baseband signal. Attenuator circuit generates an attenuated radio frequency signal according to transmitting radio frequency signal. Second signal converter circuit generates an attenuation range baseband reference signal according to attenuated radio frequency signal.

Abstract: An antenna structure includes a first signal source, a second signal source, a first radiator, a second radiator, a third radiator, a first circuit, and a second circuit. The first signal source is used to generate a first wireless signal, and the second signal source is used to generate a second wireless signal. The first radiator is coupled to the first signal source to receive the first wireless signal, and the second radiator is coupled to the second signal source to receive the second wireless signal. The first circuit has a first end coupled to the third radiator and a second end coupled to the first radiator or the first signal source. The second circuit has a first end coupled to the third radiator and a second end coupled to the second radiator or the second signal source.