Patents by Inventor Chien-Hsun Wang

Chien-Hsun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200295233
    Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first contact layer on the first semiconductor layer; a second contact layer on the second semiconductor layer, wherein the first contact layer and the second contact layer comprise a metal material other than gold (Au) or copper (Cu); a first pad on the semiconductor stack; a second pad on the semiconductor stack.
    Type: Application
    Filed: June 3, 2020
    Publication date: September 17, 2020
    Inventors: Chao-Hsing CHEN, Jia-Kuen WANG, Tzu-Yao TSENG, Bo-Jiun HU, Tsung-Hsun CHIANG, Wen-Hung CHUANG, Kuan-Yi LEE, Yu-Ling LIN, Chien-Fu SHEN, Tsun-Kai KO
  • Patent number: 10732495
    Abstract: An illumination system includes a coherent light source, a first light-combining device, an optical wavelength conversion module, and a first auxiliary light source. The coherent light source emits a coherent light beam. The first light-combining device is disposed on a transmission path of the coherent light beam. The light wavelength conversion module is disposed on a transmission path of the coherent light beam transmitted from the first light-combining device and converts the coherent light beam into a first converted light beam, and reflects the first converted light beam back to the first light-combining device. The first auxiliary light source emits a first auxiliary light beam which is transmitted to the first light-combining device. The first light-combining device combines the first auxiliary light beam and the first converted light beam. A projection apparatus and a method for driving the illumination system are also provided.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 4, 2020
    Assignee: Coretronic Corporation
    Inventors: Chi-Tang Hsieh, Ko-Shun Chen, Chi-Hsun Wang, Hao-Wei Chiu, Hou-Sheng Wang, Chien-Chung Liao, Yin-Cheng Lin, De-Sheng Yang, Ming-Tsung Weng
  • Publication number: 20200243598
    Abstract: A light-emitting device, includes a substrate, including an upper surface; a first light emitting unit and a second light emitting unit, formed on the upper surface, wherein each of the first light emitting unit and the second light emitting unit includes a lower semiconductor portion and an upper semiconductor portion; and a conductive structure electrically connecting the first light emitting unit and the second light emitting unit; wherein the lower semiconductor portion of the first light emitting unit includes a first sidewall and a first upper surface; and wherein the first side wall includes a first sub-side wall and a second sub-side wall, an obtuse angle is formed between the first sub-side wall and the first upper surface and another obtuse angle is formed between the second sub-side wall and the upper surface.
    Type: Application
    Filed: January 23, 2020
    Publication date: July 30, 2020
    Inventors: Po-Shun CHIU, Tsung-Hsun CHIANG, Liang-Sheng CHI, Jing JIANG, Jie CHEN, Tzung-Shiun YEH, Hsin-Ying WANG, Hui-Chun YEH, Chien-Fu SHEN
  • Patent number: 10714359
    Abstract: A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung Wei Cheng, Tsung-Ding Wang, Mirng-Ji Lii, Chien-Hsun Lee, Chen-Hua Yu
  • Patent number: 10707114
    Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Chun Tsai, Bing-Hung Chen, Chien-Hsun Wang, Cheng-Tung Lin, Chih-Tang Peng, De-Fang Chen, Huan-Just Lin, Li-Ting Wang, Yung-Cheng Lu
  • Patent number: 10693003
    Abstract: An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chang, Jeff J. Xu, Chien-Hsun Wang, Chih Chieh Yeh, Chih-Hsiang Chang
  • Patent number: 10685474
    Abstract: The present invention provides a method for repairing incomplete 3D depth image using 2D image information. The method includes the following steps: obtaining 2D image information and 3D depth image information; dividing 2D image information into 2D reconstruction blocks and 2D reconstruction boundaries, and corresponding to 3D reconstruction of blocks and 3D reconstruction boundaries; analyzing each 3D reconstruction block, partitioning into residual-surface blocks and repaired blocks; and proceeding at least one 3D image reconstruction, which extends with the initial depth value of the 3D depth image of each of the residual-surface block and covers all the corresponding repaired block to form a repair block and to achieve the purpose of repairing incomplete 3D depth images using 2D image information.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: June 16, 2020
    Assignee: NATIONAL CENTRAL UNIVERSITY
    Inventors: Yeh-Wei Yu, Chi-Chung Lau, Ching-Cherng Sun, Tsung-Hsun Yang, Tzu-Kai Wang, Jia-Ching Wang, Chien-Yao Wang, Kuan-Chung Wang
  • Patent number: 10680138
    Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad on the semiconductor stack; a second pad on the semiconductor stack, wherein the first pad and the second pad are separated from each other with a distance, which define a region between the first pad and the second pad on the semiconductor stack; and multiple vias penetrating the active layer to expose the first semiconductor layer, wherein the first pad and the second pad are formed on regions other than the multiple vias.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: June 9, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Bo-Jiun Hu, Tsung-Hsun Chiang, Wen-Hung Chuang, Kuan-Yi Lee, Yu-Ling Lin, Chien-Fu Shen, Tsun-Kai Ko
  • Patent number: 10651055
    Abstract: A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jen Lin, Tsung-Ding Wang, Chien-Hsun Lee
  • Patent number: 10601649
    Abstract: Stack switching detection may be provided. First, a request to connect to a server may be received by the server from a first network device. Then the server may send, in response to receiving the request, a query to the first network device for a serial number of any other network device connected to the first network device. The first network device may have a first serial number. The server may receive, from the first network device, a response to the query. The response may include a second serial number corresponding to a second network device connected to the first network device. Next, the server may determine, based on the response, that the first network device and the second network device comprise a stack unit. The server may then provision the stack unit by provisioning the first network device and provisioning the second network device through the first network device.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: March 24, 2020
    Assignee: Cisco Technology, Inc.
    Inventors: Chiragkumar P. Desai, John Manuel Lau Moy, Chien-Hsun Wang, Prakash Jhurani
  • Publication number: 20200083185
    Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 12, 2020
    Inventors: Jung Wei Cheng, Hai-Ming Chen, Chien-Hsun Lee, Hao-Cheng Hou, Hung-Jen Lin, Chun-Chih Chuang, Ming-Che Liu, Tsung-Ding Wang
  • Publication number: 20200075488
    Abstract: A method includes forming a device structure, the method including forming a first redistribution structure over and electrically connected to a semiconductor device, forming a molding material surrounding the first redistribution structure and the semiconductor device, forming a second redistribution structure over the molding material and the first redistribution structure, the second redistribution structure electrically connected to the first redistribution structure, attaching an interconnect structure to the second redistribution structure, the interconnect structure including a core substrate, the interconnect structure electrically connected to the second redistribution structure, forming an underfill material on sidewalls of the interconnect structure and between the second redistribution structure and the interconnect structure.
    Type: Application
    Filed: May 14, 2019
    Publication date: March 5, 2020
    Inventors: Jiun Yi Wu, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Shou-Yi Wang, Chien-Hsun Chen
  • Publication number: 20200063282
    Abstract: A panel to be plated is provided. The panel includes a substrate and an electric field compensation structure. The substrate includes a plurality of units to be plated each including a first pattern to be plated. The electric field compensation structure is disposed on the substrate. The electric field compensation structure includes a second pattern to be plated surrounding at least one of the units to be plated. A ratio of an area of the first pattern to be plated of the units to be plated to an area of the second pattern to be plated of the electric field compensation structure is in a range from 1:0.07 to 1:0.3.
    Type: Application
    Filed: June 20, 2019
    Publication date: February 27, 2020
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Hsun CHU, Chien-Chou TSENG, Ming-Huan YANG, Tai-Jui WANG, Yu-Hua CHUNG, Chieh-Wei FENG
  • Patent number: 10553718
    Abstract: A device structure includes: a core structure formed on a support, and a shell material formed on the core structure and surrounding at least part of the core structure. The shell material is associated with a first bandgap; the core structure is associated with a second bandgap; and the first bandgap is smaller than the second bandgap. The shell material and the core structure are configured to form a quantum-well channel in the shell material.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Carlos H. Diaz, Chun-Hsiung Lin, Huicheng Chang, Syun-Ming Jang, Chien-Hsun Wang, Mao-Lin Huang
  • Publication number: 20200035013
    Abstract: The present invention provides a method for repairing incomplete 3D depth image using 2D image information. The method includes the following steps: obtaining 2D image information and 3D depth image information; dividing 2D image information into 2D reconstruction blocks and 2D reconstruction boundaries, and corresponding to 3D reconstruction of blocks and 3D reconstruction boundaries; analyzing each 3D reconstruction block, partitioning into residual-surface blocks and repaired blocks; and proceeding at least one 3D image reconstruction, which extends with the initial depth value of the 3D depth image of each of the residual-surface block and covers all the corresponding repaired block to form a repair block and to achieve the purpose of repairing incomplete 3D depth images using 2D image information.
    Type: Application
    Filed: November 19, 2018
    Publication date: January 30, 2020
    Inventors: Yeh-Wei YU, Chi-Chung LAU, Ching-Cherng SUN, Tsung-Hsun YANG, Tzu-Kai WANG, Jia-Ching WANG, Chien-Yao WANG, Kuan-Chung WANG
  • Patent number: 10541233
    Abstract: A display device including a circuit substrate, a plurality of pixels, and a light-shielding layer is provided. The pixels include a plurality of light-emitting elements. The light-emitting elements are disposed on the circuit substrate and are electrically connected to the circuit substrate. The light-emitting elements in the pixels are arranged along an arrangement direction. The light-shielding layer is disposed on the circuit substrate and has a plurality of pixel apertures. The pixels are disposed in a corresponding pixel aperture. The light-shielding layer includes a plurality of first light-shielding patterns extending in the arrangement direction and a plurality of second light-shielding patterns connected to the first light-shielding patterns. The extending direction of the second light-shielding patterns is different from the extending direction of the first light-shielding patterns.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: January 21, 2020
    Assignees: Industrial Technology Research Institute, Macroblock, Inc.
    Inventors: Po-Hsun Wang, Chia-Hsin Chao, Ming-Hsien Wu, Yen-Hsiang Fang, Chien-Chung Lin, Ming-Jer Kao, Feng-Pin Chang
  • Patent number: 10522486
    Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung Wei Cheng, Hai-Ming Chen, Chien-Hsun Lee, Hao-Cheng Hou, Hung-Jen Lin, Chun-Chih Chuang, Ming-Che Liu, Tsung-Ding Wang
  • Patent number: 10515931
    Abstract: An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Ding Wang, Chien-Hsun Lee
  • Patent number: 10483132
    Abstract: A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jen Lin, Tsung-Ding Wang, Chien-Hsun Lee
  • Publication number: 20190346661
    Abstract: An optical imaging lens assembly includes five lens elements, which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof. The third lens element has negative refractive power. The fifth lens element has negative refractive power.
    Type: Application
    Filed: October 3, 2018
    Publication date: November 14, 2019
    Applicant: LARGAN PRECISION CO.,LTD.
    Inventors: Kuan-Ting YEH, Kuo-Jui WANG, Chien-Hsun WU, Wei-Yu CHEN, Po-Lun HSU