Abstract: Transistor devices and methods for forming transistor devices are provided. A transistor device includes a semiconductor substrate and a device layer. The device layer includes a source region and a drain region connected by a suspended nanowire channel. First and second etch stop layers are respectively arranged beneath the source region and the drain region. Each of the etch stop layers forms a support structure interposed between the semiconductor substrate and the respective source and drain regions.

Abstract: An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.

Abstract: A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.

Abstract: An integrated circuit transistor structure includes a semiconductor substrate, a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first SiGe layer has a Ge concentration of 50 percent or more.

Abstract: A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method of forming a semiconductor device includes receiving a substrate and forming a termination layer on a top surface of the substrate. The termination layer includes at least one of hydrogen, deuterium, or nitrogen. The method further includes depositing a dielectric layer on the termination layer such that the depositing of the dielectric layer does not disrupt the termination layer. The termination layer may be formed by a first deposition process that deposits a first material of the termination layer and a subsequent deposition process that introduces a second material of the termination layer into the first material. The termination layer may also be formed by a single deposition process that deposits both a first material and a second material of the termination layer.

Abstract: An integrated circuit includes a core area. The core area has at least one edge region and a plurality of transistors disposed in the edge region. A plurality of dummy structures are disposed outside the core area and adjacent to the at least one edge region. Each channel of the transistors in a channel width direction faces at least one of the dummy structures.

Abstract: A portable NDIR breath acetone measurement apparatus includes a portable housing formed with an optical cavity, which is housed in a receiving chamber for containing a gas sample taken from an exhaled breath of a human subject. A control unit controls the temperature in the receiving chamber to a desired temperature, and controls an IR emitter disposed in the receiving chamber to stably emit IR spectrum radiation propagating along a zigzag path toward an IR detector, which is operated at the desired temperature to generate, in response to detection of the IR spectrum radiation, an IR signal that is processed and analyzed by a signal processing unit to obtain a measurement result indicative of the concentration of acetone gas contained in the gas sample.

Abstract: A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; forming a barrier layer between the channel layer and the substrate; forming a recess that extends into the barrier layer through the channel layer; and forming a source layer in the recess.

Abstract: A method for an apparatus to monitor an appliance includes receiving information about a translation of a control knob of the appliance along an axis and a rotation of the control knob around the axis, determining if a first event has occurred based on the information, and, when the first event has occurred, starting a timer and determining if a second event has occurred based on the information before the timer reaches a time interval. The method further includes, when the second event does not occur before the timer reaches the time interval, triggering an alert.

Abstract: Structures and methods are provided for forming bottom source/drain contact regions for nanowire devices. A nanowire is formed on a substrate. The nanowire extends substantially vertically relative to the substrate and is disposed between a top source/drain region and a bottom source/drain region. A first dielectric material is formed on the bottom source/drain region. A second dielectric material is formed on the first dielectric material. A first etching process is performed to remove part of the first dielectric material and part of the second dielectric material to expose part of the bottom source/drain region. A second etching process is performed to remove part of the first dielectric material under the second dielectric material to further expose the bottom source/drain region. A first metal-containing material is formed on the exposed bottom source/drain region. Annealing is performed to form a bottom contact region.

Abstract: A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins.

Abstract: A semiconductor device includes a source/drain region, a barrier layer, and an interlayer dielectric. The barrier layer surrounds the source/drain region. The interlayer dielectric surrounds the barrier layer. As such, the source/drain region can be protected by the barrier layer from oxidation during manufacturing of the semiconductor device, e.g., the formation of the interlayer dielectric.

Abstract: A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method comprises receiving a substrate, the substrate containing a semiconductor; preparing a surface of the substrate; forming a termination layer bonded to the semiconductor at the surface of the substrate; and depositing a dielectric layer above the termination layer, the depositing configured to not disrupt the termination layer. The forming of the termination layer may be configured to produce the termination layer having a single layer of oxygen atoms between the substrate and the dielectric layer.

Abstract: This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins.

Abstract: A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; forming a barrier layer between the channel layer and the substrate; forming a recess that extends into the barrier layer through the channel layer; and forming a source layer in the recess.

Abstract: Transistor devices and methods for forming transistor devices are provided. A transistor device includes a semiconductor substrate and a device layer. The device layer includes a source region and a drain region connected by a suspended nanowire channel. First and second etch stop layers are respectively arranged beneath the source region and the drain region. Each of the etch stop layers forms a support structure interposed between the semiconductor substrate and the respective source and drain regions.

Abstract: This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins. Accordingly, compared to conventional methods limited by fin height from the STI, the double STI recess method provides greater fin height, which is a larger process window for HGAA nanowire formation, to easily produce multi-stack HGAA nanowires with high current density. The number of layers used in the multi-stack HGAA nanowires is not limited and may vary based on different designs.

Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.

Abstract: This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins. Accordingly, compared to conventional methods limited by fin height from the STI, the double STI recess method provides greater fin height, which is a larger process window for HGAA nanowire formation, to easily produce multi-stack HGAA nanowires with high current density. The number of layers used in the multi-stack HGAA nanowires is not limited and may vary based on different designs.