Patents by Inventor Chien-Hsun Wang

Chien-Hsun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8633076
    Abstract: A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: January 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Wang, Chih-Sheng Chang, Yi-Tang Lin
  • Publication number: 20140013288
    Abstract: A method of generating a layout for a device includes receiving a first layout including a plurality of active regions, each active region of the plurality of active regions having sides. The method further includes defining a plurality of elongate mandrels that each extend in a first direction and are spaced apart from one another in a second direction perpendicular to the first direction. The method further includes for each adjacent pair of partially-parallel active regions of the plurality of active regions having a minimum distance less than a specified minimum spacing, connecting at least a portion of nearest ends of pairs of elongate mandrels, each mandrel of a pair from a different active region. The method further includes generating a second layout including a plurality of elongate mandrels in the plurality of active regions, and connective elements between active regions of at least one adjacent pair of active regions.
    Type: Application
    Filed: September 4, 2013
    Publication date: January 9, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun WANG, Chih-Sheng CHANG, Yi-Tang LIN, Ming-Feng SHIEH
  • Patent number: 8623728
    Abstract: A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chang, Jeff J. Xu, Chien-Hsun Wang, Chih Chieh Yeh, Chih-Hsiang Chang
  • Patent number: 8525267
    Abstract: A semiconductor FinFET device includes a plurality of gate lines formed in a first direction, and two types of fin structures. A first type of fin structures is formed in a second direction, and a second type of fin structures formed perpendicular to the first type of fin structures. A contact hole couples to one or more of the second type of fin structures.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: September 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Wang, Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh
  • Patent number: 8526315
    Abstract: A method in one embodiment includes allocating, by a node of a network, a flow label attribute identifying a media flow associated with a Session Description Protocol (SDP) media session. The media flow is between a sender and receiver nodes over a media transmission path of the network. The node further specifying a flow state attribute to generate media flow information and communicating the flow label and the flow state attribute to downstream nodes in the media transmission path. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: September 3, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Xiaode Xu, Chien-Hsun Wang
  • Patent number: 8502502
    Abstract: An electricity storing device includes a high-voltage terminal, a low-voltage terminal, a plurality of rechargeable battery modules, a plurality of first switches each coupled between one rechargeable battery module and the high-voltage terminal, a plurality of second switches each coupled between one rechargeable battery module and the low-voltage terminal, a plurality of third switches each coupled between two of the rechargeable battery modules, and a control module for outputting a control command to control couplings of the plurality of first switches, the plurality of second switches and the plurality of third switches.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: August 6, 2013
    Assignee: Wistron Corporation
    Inventors: Shyh-Ching Huang, Yu-You Ting, Chien-Hsun Wang
  • Patent number: 8486769
    Abstract: A method for forming a plurality of fins on a semiconductor substrate includes depositing a spacer layer to fill in gaps between the plurality of fins, the fins comprising a first material and the spacer layer comprising a second material. A first area is defined where the fins need to be broadened and a second area is defined where the fins do not need to be broadened. The method also includes patterning the spacer layer to remove spacers in the first area where the fins need to be broadened and applying an epitaxy process at a predetermined rate to grow a layer of the first material on fins in the first area. The spacer layer is removed in the second area where the fins do not need broadening.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: July 16, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Wang, Chih-Sheng Chang, Ming-Feng Shieh
  • Patent number: 8395195
    Abstract: An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: March 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chang, Jeffrey Junhao Xu, Chien-Hsun Wang, Chih-Hsiang Chang
  • Publication number: 20120126325
    Abstract: A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins.
    Type: Application
    Filed: November 23, 2010
    Publication date: May 24, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Wang, Chih-Sheng Chang, Yi-Tang Lin
  • Publication number: 20120126375
    Abstract: A method for forming a plurality of fins on a semiconductor substrate includes depositing a spacer layer to fill in gaps between the plurality of fins, the fins comprising a first material and the spacer layer comprising a second material. A first area is defined where the fins need to be broadened and a second area is defined where the fins do not need to be broadened. The method also includes patterning the spacer layer to remove spacers in the first area where the fins need to be broadened and applying an epitaxy process at a predetermined rate to grow a layer of the first material on fins in the first area. The spacer layer is removed in the second area where the fins do not need broadening.
    Type: Application
    Filed: November 19, 2010
    Publication date: May 24, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Wang, Chih-Sheng Chang, Ming-Feng Shieh
  • Publication number: 20120126326
    Abstract: A semiconductor FinFET device includes a plurality of gate lines formed in a first direction, and two types of fin structures. A first type of fin structures is formed in a second direction, and a second type of fin structures formed perpendicular to the first type of fin structures. A contact hole couples to one or more of the second type of fin structures.
    Type: Application
    Filed: November 23, 2010
    Publication date: May 24, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Wang, Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh
  • Publication number: 20120124528
    Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. A plurality of elongate mandrels is defined in a plurality of active regions. Where adjacent active regions are partially-parallel and within a specified minimum spacing, connective elements are added to a portion of the space between the adjacent active regions to connect the mandrel ends from one active region to another active region.
    Type: Application
    Filed: September 8, 2011
    Publication date: May 17, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun WANG, Chih-Sheng CHANG, Yi-Tang LIN, Ming-Feng SHIEH
  • Patent number: 8145789
    Abstract: A cluster console user interface provides a single console control point for a network device cluster comprising a first switch device, a plurality of active routers, one or more standby routers, and a second switch device. Using the cluster console, a network administrator can perform various operations with respect to the cluster as a whole, without knowing identity information for particular network routers serving as active or standby, or for the switch devices.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: March 27, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Arnold Stamler, Tohru Kao, Pratima Aiyagari, Chien-Hsun Wang
  • Publication number: 20110305933
    Abstract: An electricity storing device includes a high-voltage terminal, a low-voltage terminal, a plurality of rechargeable battery modules, a plurality of first switches each coupled between one rechargeable battery module and the high-voltage terminal, a plurality of second switches each coupled between one rechargeable battery module and the low-voltage terminal, a plurality of third switches each coupled between two of the rechargeable battery modules, and a control module for outputting a control command to control couplings of the plurality of first switches, the plurality of second switches and the plurality of third switches.
    Type: Application
    Filed: October 15, 2010
    Publication date: December 15, 2011
    Inventors: Shyh-Ching Huang, Yu-You Ting, Chien-Hsun Wang
  • Publication number: 20110227188
    Abstract: An integrated circuit includes a core area. The core area has at least one edge region and a plurality of transistors disposed in the edge region. A plurality of dummy structures are disposed outside the core area and adjacent to the at least one edge region. Each channel of the transistors in a channel width direction faces at least one of the dummy structures.
    Type: Application
    Filed: March 17, 2010
    Publication date: September 22, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun WANG, Chih-Sheng CHANG, Hsien-Hui MENG
  • Publication number: 20110193178
    Abstract: An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width.
    Type: Application
    Filed: February 9, 2010
    Publication date: August 11, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chang, Jeffrey Junhao Xu, Chien-Hsun Wang, Chih-Hsiang Chang
  • Publication number: 20110024804
    Abstract: A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation.
    Type: Application
    Filed: July 7, 2010
    Publication date: February 3, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hao CHANG, Jeff J. XU, Chien-Hsun WANG, Chih Chieh YEH, Chih-Hsiang CHANG
  • Publication number: 20090052458
    Abstract: A method in one embodiment includes allocating, by a node of a network, a flow label attribute identifying a media flow associated with a Session Description Protocol (SDP) media session. The media flow is between a sender and receiver nodes over a media transmission path of the network. The node further specifying a flow state attribute to generate media flow information and communicating the flow label and the flow state attribute to downstream nodes in the media transmission path. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
    Type: Application
    Filed: August 23, 2007
    Publication date: February 26, 2009
    Applicant: Cisco Technology, Inc.
    Inventors: Xiaode Xu, Chien-Hsun Wang