Abstract: In a report generation system and method, one or more test parameters, a measured characteristic, and value ranges of the measured characteristic are set. Values of the one or more test parameters and the measured characteristic are retrieved from measurement data. The values are arranged to create a report of the measured characteristic versus the one or more test parameters. Each of the values of the measured characteristic is classified into one of the value ranges. The report is marked according to the value ranges of the values of the measured characteristic.

Abstract: A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures.

Abstract: A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less than a length of the ONO layer. Two buried diffusion spacers are formed beside two sidewalls of the polysilicon gate and over the ONO layer. Two buried diffusion regions are implanted on the silicon substrate next to the two buried diffusion spacers. The two buried diffusion regions are then annealed such that the approximate interfaces of the buried diffusion regions are under the sidewalls of the polysilicon gate. The structure of a nitride read only memory device with buried diffusion spacers is also described.

Abstract: The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad.

Abstract: Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

Abstract: A printed circuit board (PCB) includes a differential pair having a first differential trace and a second differential trace, a first via having an upper cap and a lower cap, and a second via having an upper cap and a lower cap. The first differential trace includes a first segment and a second segment, the second differential trace includes a third segment and a fourth segment. The first and the third segments are electrically coupled to the upper caps of the first and the second vias respectively. The second and the fourth segments are electrically coupled to the lower caps of the first and the second vias respectively. The first and the third segments extend from corresponding upper caps in different directions, the second and the fourth segments extend from corresponding lower caps in different directions.

Abstract: A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less than a length of the ONO layer. Two buried diffusion spacers are formed beside two sidewalls of the polysilicon gate and over the ONO layer. Two buried diffusion regions are implanted on the silicon substrate next to the two buried diffusion spacers. The two buried diffusion regions are then annealed such that the approximate interfaces of the buried diffusion regions are under the sidewalls of the polysilicon gate. The structure of a nitride read only memory device with buried diffusion spacers is also described.

Abstract: An image deblurring system deblurs motion blurred images of a video stream captured from a moving object. An image deblurring method selects a blurred image from the video stream, selects blurred pixels from the blurred image, and calculates a movement offset for each of the blurred pixels according to coordinates of the blurred pixel in a frequency domain during the movement of the moving object. The method generates a point spread function according to the movement offset, and generates an image conversion formula according to the point spread function. The method converts each of the blurred pixels into a sharp pixel according to the image conversion formula, and generates a sharp image based on all of the sharp pixels.

Abstract: One aspect of the present disclosure relates to a common repair structure for repairing scanning and/or data line defects in a liquid crystal display panel. In one embodiment, the common repair structure includes a plurality of “H” shaped structures, where each “H” shaped structure is placed over a corresponding segment of two neighboring scanning lines located between and associated with two neighboring pixels along the second direction or a corresponding segment of two neighboring data lines located between and associated with two neighboring pixels along the first direction.

Abstract: A printed circuit board includes a number of signal layers, a number of ground layers, a first transmission line, a second transmission line, a first via, and a second via. The first transmission is located on one of the number of signal layers. The second transmission line is located on another of the number of signal layers. The first and second vias pass through the printed circuit board. The first via is electrically coupled to the first and second transmission lines, and is isolated from the number of ground layers. The second via is electrically coupled to one or more of the number of ground layers, and is isolated from the other of the number of ground layers to increase an inductance, thus compensating capacitive nature of an open stub and improving signal integrity.

Abstract: A design method of printed circuit boards includes the following steps. First, simulate a printed circuit board including power layers, and vias connected to all the power layers. Then, change connections of the vias that tend to draw too much current to be connected to fewer power layers, than the vias that tend to draw less current. Repeat adjusting connections of the vias until all vias draw a similar amount of current such that no via draws more current than an upper limit the vias are designed for. Finally, according to the results, design/fabricate a PCB with vias respectively insulated, as needed, from the power layers that do not need to be connected to the vias.

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate containing a semiconductor component and a conductive pad thereon. A through hole penetrates the semiconductor substrate from a backside thereof to expose the conductive pad. A redistribution layer is below the backside of the semiconductor substrate and electrically connected to the conductive pad in the through hole. A conductive trace layer is below the redistribution layer and extended along a sidewall of the semiconductor substrate to electrically contact with an edge of the redistribution layer.

Abstract: A performance evaluation system for a multiple-input multiple-output (MIMO) antenna system receives simulation parameters from an input device, and simulates a MIMO antenna system accordingly. A method, also provided, further evaluates performance of the simulated MIMO antenna system when a series of radio frequency (RF) signals are transmitted through the MIMO antenna system, and displays a performance analysis result of the MIMO antenna system on a display device for evaluation of the performance of the simulated MIMO antenna system.

Abstract: An automatic scan and mark apparatus has a machine tool, a location detection module, a laser detector, an ink jet and a control computer. The machine tool has a movable module and a stage. The stage mounts and holds a specimen having a scraped surface. The control computer controls the location detection module to determine a position of the movable module, controls the laser detector to detect a surface morphology of the scraped surface in a measurement range, and activates the ink jet to eject inks on high points of the scraped surface of the specimen. Thus, the surface morphology is built automatically and high points are screened out and marked by colored ink. Manufacturer may easily redo scraping of determined high points based on the marked location on the specimen without burdensome measurement.

Abstract: A signal transmission apparatus includes a first ground layer, a second ground layer and a band pass filter. The band pass filter includes a first transmission line positioned in a void defined in the first ground layer and a second transmission line positioned in a void defined in the second ground layer. Each of the first transmission line and the second transmission line includes a coil with a plurality of turns spirally extending in the same plane, a gasket extending from the coil and located in the center of the coil, and a signal terminal extending from extremity of the coil. According to employing the band pass filter, the signal transmission apparatus has filtering function, therefore, quality of signals transmitted through the signal transmission apparatus is improved.

Abstract: The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region.

Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.

Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.

Abstract: A printed circuit board includes a first layer, a second layer, a number of vias each passing through the first and second layers, and a number of transmission lines. Each transmission line is connected between bonding pads of the two of the number of vias to form a helical-shaped transmission path by the vias and the transmission lines. As a result, the printed circuit board can generate inductive effect.

Abstract: A detecting assembly for multi-axis machine tools having a spindle and a turntable and has a detector, a lens device and a computer. The detector is connected to the spindle and has a mounting frame and two detecting segments. The mounting frame is connected to the spindle and has a connecting rod, a bottom board and multiple mounting boards. The detecting segments are mounted on the mounting boards and each has a light source and a sensor. The lens device is mounted on the turntable, extends into the detector and has a supporting shaft and a spherical lens. The spherical lens is mounted on an upper end of the supporting shaft to align light emitted from the light sources with corresponding sensors via the spherical lens. The computer is electrically connected to the detector to receive signals of the detecting segments of the detector and has a signal processor.