Abstract: An enclosure of an electronic device includes a plate. The plate defines a number of through holes. A number of shields extend from the plate corresponding to the through holes. Each shield extends outwards from the outer surface of the plate, surrounding and partly covering a corresponding through hole. The enclosure with the shields can shield the electronic device from EMI.

Abstract: In a method for testing serial attached SCSI (SAS) ports of a server using a computing device, the computing device connects to an oscilloscope and a mechanical arm that is equipped with a test fixture having a probe. The mechanical arm controls the probe to be plugged into one of the SAS ports. The method adjusts an intensity grade of the SAS signals through the SAS port, and controls the SAS port to generate a SAS signal corresponding to the intensity grade. The test fixture obtains the SAS signal from the SAS port, and the oscilloscope measures test parameters of the SAS signal. The method analyzes values of the test parameters to find an optimal SAS signal, determines an intensity grade of the optimal SAS signal as a driving parameter of the SAS port, and accordingly generates a test report of the SAS ports.

Abstract: An embodiment of the invention provides a chip package which includes a substrate having an upper surface and a lower surface and having at least a side surface, and at least a trench extending from the upper surface towards the lower surface and extending from the side surface towards an inner portion of the substrate, wherein a width of the trench near the upper surface is not equal to a width of the trench near the lower surface, and at least an insulating layer located on a sidewall of the trench, and at least a conducting pattern located on the insulating layer, wherein the side surface is separated from the conducting pattern in the trench by a predetermined distance such that a portion of the insulating layer is exposed, and at least a conducting region electrically connected to the conducting pattern.

Abstract: A chip package structure and a method for forming the chip package structure are disclosed. At least a block is formed on a surface of a cover, the cover is mounted on a substrate having a sensing device formed thereon for covering the sensing device, and the block is disposed between the cover and the sensing device. In the present invention, the block is mounted on the cover, there is no need to etch the cover to form a protruding portion, and thus the method of the present invention is simple and has low cost.

Abstract: The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region.

Abstract: An enclosure of an electronic device includes a plate. The plate defines a number of through holes. Each through hole has a pair of tabs connected to each other and with the through hole. Each pair of tabs are slantingly bent towards an inside of the enclosure. The enclosure with the shields can shield the electronic device from electro-magnetic interference.

Abstract: An embodiment of the present invention provides a manufacturing method of an interposer including: providing a semiconductor substrate having a first surface, a second surface and at least a through hole connecting the first surface to the second surface; electrocoating a polymer layer on the first surface, the second surface and an inner wall of the through hole; and forming a wiring layer on the electrocoating polymer layer, wherein the wiring layer extends from the first surface to the second surface via the inner wall of the through hole. Another embodiment of the present invention provides an interposer.

Abstract: An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate has at least one opening penetrating through the second substrate, and the at least one opening defines a plurality of conducting regions electrically insulated from each other in the second substrate; a first insulating layer disposed on a side of the first substrate and filling in the at least one opening of the second substrate; a carrier substrate disposed on the second substrate; a second insulating layer disposed on a surface and a sidewall of the carrier substrate; and a conducting layer disposed on the second insulating layer on the carrier substrate and electrically contacting with one of the conducting regions.

Abstract: An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate has at least one opening penetrating through the second substrate, and the at least one opening defines a plurality of conducting regions electrically insulated from each other in the second substrate; a carrier substrate disposed on the second substrate; an insulating layer disposed on a surface and a sidewall of the carrier substrate, wherein the insulating layer fills the at least one opening of the second substrate; and a conducting layer disposed on the insulating layer on the carrier substrate and electrically contacting with one of the conducting regions.

Abstract: Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

Abstract: The invention provides A chip package, comprising: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region, and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; and a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures, wherein the heavily doped regions are disposed in a carrier substrate which is bonded to the first surface of the semiconductor substrate.

Abstract: A printed circuit board includes a signal layer and a ground layer adjacent to the signal layer. The signal layer includes a pair of differential transmitting lines. The ground layer includes a common mode filter formed by hollow spiral patterns in the ground layer. The common mode filter includes two filter portions respectively arranged at opposite sides of a projection of the pair of differential transmitting lines onto the ground layer. Hollowed areas of the two filter portions are bridged by a void.

Abstract: An enclosure includes a plate. The plate defines a number of through holes. A hollow shield extends from the edges bounding each through hole. A top side of the shield opposite to the plate is smaller than a bottom side of the shield which is connected to the edges of the through hole. The enclosure can better shield electromagnetic interference (EMI) from the electronic device.

Abstract: One aspect of the present disclosure relates to a common repair structure for repairing scanning and/or data line defects in a liquid crystal display panel. In one embodiment, the common repair structure includes a plurality of “H” shaped structures, where each “H” shaped structure is placed over a corresponding segment of two neighboring scanning lines located between and associated with two neighboring pixels along the second direction or a corresponding segment of two neighboring data lines located between and associated with two neighboring pixels along the first direction.

Abstract: An exemplary high speed data storage system includes hard disks, a first control panel, a second control panel and a midplane interconnected between each of the first and second control panels and the hard disks. Each of the first and second control panels includes a control chip and a connector. First and second printed circuit wires corresponding to the hard disks are layered on the first and second control panels for electrically connecting the control chip with the connector, respectively. The first printed circuit wires of the first control panel and the second printed circuit wires of the second control panel are arranged symmetrically with respect to each other, and an order of stacking circuit layers of the first printed circuit wires of the first control panel is the reverse of an order of stacking of circuit layers of the second printed circuit wires of the second control panel.

Abstract: A printed circuit board includes a number of signal layers, a number of ground layers, a first transmission line, a second transmission line, a first via, and a second via. The first transmission is located on one of the number of signal layers. The second transmission line is located on another of the number of signal layers. The first and second vias pass through the printed circuit board. The first via is electrically coupled to the first and second transmission lines, and is isolated from the number of ground layers. The second via is electrically coupled to one or more of the number of ground layers, and is isolated from the other of the number of ground layers to increase an inductance, thus compensating capacitive nature of an open stub and improving signal integrity.

Abstract: A printed circuit board includes a first signal layer, a second signal layer, and a dielectric layer sandwiched between the first signal layer and the second signal layer. The first signal layer includes two pads. The second signal layer includes two conducting pieces connected to two signal traces. The shape and material of the pads are the same as the shape and material of the conducting pieces. The projections of the pads on the second signal layer are overlapping with the conducting pieces.

Abstract: One aspect of the present disclosure relates to a common repair structure for repairing scanning and/or data line defects in a liquid crystal display panel. In one embodiment, the common repair structure includes a plurality of “H” shaped structures, where each “H” shaped structure is placed over a corresponding segment of two neighboring scanning lines located between and associated with two neighboring pixels along the second direction or a corresponding segment of two neighboring data lines located between and associated with two neighboring pixels along the first direction.

Abstract: A printed circuit board includes a signal layer and a ground layer adjacent to the signal layer. The signal layer includes a pair of differential transmission lines. The ground layer includes a first void, a second void, a third void, and a common mode filter. The first void and the second void are respectively arranged at opposite sides of a projection of the pair of differential transmission lines on the ground layer, and are bridged with the third void. The common mode filter includes a first filter portion positioned in the first void, and a second filter portion positioned in the second void. Each of the first and second filter portions includes a number of coils arranged side by side along a direction parallel to the projection of the pair of differential transmission lines.

Abstract: An enclosure includes a plate. The plate defines a number of through holes. A first shield extends from an edge bounding each through hole. A second shield extends from the edge bounding each through hole, opposite to the first shields. Each through hole is partially covered by a corresponding first shield and a corresponding second shield. The enclosure with the shields can shield the electronic device from electromagnetic interference.