Abstract: An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.

Abstract: An accessing device communicating with a host device and including a connector, a storage unit and a control unit is disclosed. The connector connects to the host device. The storage unit stores data. The control unit communicates with the storage unit according to a first communication protocol and communicates with the host device via the connector according to a second communication protocol. The control unit determines the kind of the second communication protocol according to selection information.

Abstract: An electronic device is provided. When the electronic device is at a power exhaustion state and a first external device with a charging function is coupled to a connection interface to provide a first supply voltage to a power pin of the connection interface, a voltage regulation unit transforms the first supply voltage to a first operation voltage, and a storage unit powered by the first operation voltage outputs device information of the electronic device to the first external device through a signal transmitting/receiving pin set of the connection interface. When the first external device provides a second supply voltage to the power pin in response to the device information, the electronic device enters a charging mode. In the charging mode, the charging unit provides a charging voltage according to the second supply voltage to charge the battery unit and provides a second operation voltage to a processing unit.

Abstract: An embodiment of the present invention provides a manufacturing method of an interposer including: providing a semiconductor substrate having a first surface, a second surface and at least a through hole connecting the first surface to the second surface; electrocoating a polymer layer on the first surface, the second surface and an inner wall of the through hole; and forming a wiring layer on the electrocoating polymer layer, wherein the wiring layer extends from the first surface to the second surface via the inner wall of the through hole. Another embodiment of the present invention provides an interposer.

Abstract: An electronic device includes a connection interface, a voltage regulation unit, a storage unit, a charging unit, a processing unit, and a switching unit. The switching unit is coupled to the storage unit, the processing unit, and the connection interface. When the electronic device is in a power-exhaustion state and an external device having a charging function is coupled to the connection interface to provide a first supplying voltage to a power pin of the connection interface, the voltage regulation unit transforms the first supplying voltage to a first operation voltage to power the storage unit and the switching unit, and the switching unit couples the storage unit to the connection interface to transmit device information to the external device. When the external device provides a second supplying voltage to the power pin in response to the device information, the electronic device is in a charging state.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a drain region located in the semiconductor substrate; a source region located in the semiconductor substrate; a gate located on the semiconductor substrate or at least partially buried in the semiconductor substrate, wherein a gate dielectric layer is between the gate and the semiconductor substrate; a drain conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the drain region; a source conducting structure disposed on the second surface of the semiconductor substrate and electrically connected to the source region; and a gate conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the gate.

Abstract: A package structure which includes a non-conductive substrate, a conductive element, a passivation, a jointed side, a conductive layer, a solder and a solder mask is disclosed. The conductive element is disposed on a surface of the non-conductive substrate and consists of a passive element and a corresponding circuit. The passivation completely covers the conductive element and the non-conductive substrate so that the conductive element is sandwiched between the passivation and the non-conductive substrate. The conductive layer covers the jointed side which exposes part of the corresponding circuit, extends beyond the jointed side and is electrically connected to the corresponding circuit. The solder mask which completely covers the jointed side and the conductive layer selectively exposes the solder which is disposed outside the jointed side and electrically connected to the conductive layer.

Abstract: A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.

Abstract: A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less than a length of the ONO layer. Two buried diffusion spacers are formed beside two sidewalls of the polysilicon gate and over the ONO layer. Two buried diffusion regions are implanted on the silicon substrate next to the two buried diffusion spacers. The two buried diffusion regions are then annealed such that the approximate interfaces of the buried diffusion regions are under the sidewalls of the polysilicon gate. The structure of a nitride read only memory device with buried diffusion spacers is also described.

Abstract: Embodiments of the present invention provide a chip package including: a substrate having a first surface and a second surface; a device region located in the substrate; a conducting pad structure disposed on the substrate and electrically connected to the device region; a spacer layer disposed on the first surface of the substrate; a second substrate disposed on the spacer layer, wherein a cavity is created and surrounded by the second substrate, the spacer layer, and the substrate on the device region; and a through-hole extending from a surface of the second substrate towards the substrate, wherein the through-hole connects to the cavity.

Abstract: A method for reducing audible noise of a power supply provides a PWM signal for controlling a power converter. First, a feedback voltage is produced by detecting an output voltage of the power converter. Afterward, a burst-in voltage and a burst-out voltage are set. Afterward, a voltage level of the burst-in voltage or a voltage level of the burst-out voltage is dynamically varied. Afterward, the PWM signal is switched off when the feedback voltage is less than the burst-in voltage. Final, the PWM signal is switched on when the feedback voltage is greater than the burst-out voltage.

Abstract: A manufacturing-process equipment has a platform assembly, a measurement feedback assembly and a laser-working assembly. The platform assembly has a base and a hybrid-moving platform. The base has a mounting frame. The hybrid-moving platform is mounted on the base and has a long-stroke moving stage and a piezo-driven micro-stage. The long-stroke moving stage has a benchmark set and a driving device. The piezo-driven micro-stage is connected to the long-stroke moving stage and has a working platform. The measurement feedback assembly is securely mounted on the platform assembly and has a laser interferometer, a reflecting device and a signal-receiving device. The laser-working assembly is mounted on the platform assembly, is electrically connected to the measurement feedback assembly and has a laser direct-writing head, a controlling interface device and a positioning interface device.

Abstract: A host device includes a processing core, a switch, and a host-end universal serial bus (USB) connector. The processing core provides a display signal and a USB signal to the switch. The host-end USB connector is selectively connected to a video USB (VUSB) display device and a USB peripheral device. The processing core has the switch controlled to output the display signal via the host-end USB connector, when the host-end USB connector is connected to a VUSB display device. The processing core has the switch controlled to output the USB signal via the host-end USB connector, when the host-end USB connector is connected to a USB peripheral device.

Abstract: An image deblurring system deblurs motion blurred images of a video stream captured from a moving object. An image deblurring method selects a blurred image from the video stream, selects blurred pixels from the blurred image, and calculates a movement offset for each of the blurred pixels according to coordinates of the blurred pixel in a frequency domain during the movement of the moving object. The method generates a point spread function according to the movement offset, and generates an image conversion formula according to the point spread function. The method converts each of the blurred pixels into a sharp pixel according to the image conversion formula, and generates a sharp image based on all of the sharp pixels.

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate containing a semiconductor component and a conductive pad thereon. A through hole penetrates the semiconductor substrate from a backside thereof to expose the conductive pad. A redistribution layer is below the backside of the semiconductor substrate and electrically connected to the conductive pad in the through hole. A conductive trace layer is below the redistribution layer and extended along a sidewall of the semiconductor substrate to electrically contact with an edge of the redistribution layer.

Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.

Abstract: An electronic component package is described. The electronic component package includes a first electronic component package module mounted on a surface of a packaging layer. A second electronic component package module laminated on a bottom of the first electronic component package module is mounted on a surface of a packaging layer. The first and second electronic component package modules respectively include at least two semiconductor chips laminated. A first redistribution layer is between the first and the second electronic component package modules, electrically connected to the first and the second electronic component package modules. A conductive bump is mounted on a bottom of the second electronic component package module, electrically connected to the second electronic component package module.

Abstract: An enclosure of an electronic device includes a ventilation plate. The ventilation plate is a grid including a number of crisscrossed connection bars and a number of through holes defined by the connection bars. A tab is formed at each of the connection bars bounding each of the through holes. The tabs are substantially angled from a plane of the grid to elongate a path electromagnetic signals must travel to pass through the ventilation plate. The enclosure with the shields can shield the electronic device from EMI.

Abstract: An accessing device communicating with a host device and including a connector, a storage unit and a control unit is disclosed. The connector connects to the host device. The storage unit stores data. The control unit communicates with the storage unit according to a first communication protocol and communicates with the host device via the connector according to a second communication protocol. The control unit determines the kind of the second communication protocol according to selection information.

Abstract: A power supply system includes an output node, an internal power supply unit, a boost storage unit, a charging path unit, and a discharging path unit. The output node is coupled to a load device. The internal power supply unit includes a gold capacitor unit for storing an internal storage voltage. The charging path unit is turned on in a charging period to store a boost supply voltage in the boost storage unit. The discharging path is turned on in a discharging period to provide a power signal for drive the load device according to the internal storage voltage and the boost supply voltage. The charging and discharging periods are non-overlapping.