Abstract: A power adjustment system and a power adjustment method of an autonomous mobile device are provided. In the power adjustment method, two first current control signals respectively transmitted to two drivers are outputted by a control module. A tilt angle of the autonomous mobile device is detected by an inertial measurement module. A travel route is planned by a navigation module, and the control module obtains a steering angle of the autonomous mobile device during a traveling process. According to different weight values of the autonomous mobile device stored in a database module, a weight of the autonomous mobile device is estimated by the control module. According to the two first current control signals and the weight, the steering angle, and the tilt angle of the autonomous mobile device, two second current control signals respectively transmitted to the two drivers are outputted by the control module.

Abstract: A semiconductor device having source and drain regions in a semiconductor substrate, a transistor including a gate electrode over the semiconductor substrate, an isolation structure in the semiconductor substrate adjacent to the transistor, a first inter-dielectric layer (ILD) material over the isolation structure, and a capacitor film stack over the first ILD material that includes an isolation plate over and covering a capacitor plate, and a contact to the capacitor plate.

Abstract: A touch sensor comprises a first electrode, a second electrode arranged spaced apart from the first electrode, and an insulator arranged between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode is energized, and an energy difference exists between the first electrode and the second electrode. At least one of the first electrode and the second electrode is a stressed electrode. When the stressed electrode is not stressed, no electrical signal is generated, and when the stressed electrode is stressed, the stressed electrode deforms at a stressed point and changes the distance between the stressed point and the other electrode to generate a tunneling current, and the touch sensor generates the electrical signal according to whether the tunneling current is generated. Therefore, the invention solves a limitation of the conventional touch sensor in touching and provides good touching sensitivity.

Abstract: An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

Abstract: A method of remotely modifying a basic input/output system (BIOS) configuration setting includes steps of: transmitting, by a remote computer, a modification instruction to a cloud server; transmitting, by the cloud server to a POS system, a new configuration value of the BIOS configuration setting contained in the modification instruction; determining, by an embedded controller of the POS system, whether the new configuration value is identical to an original configuration value of the BIOS configuration setting; and by the embedded controller when a result of the determination is negative, updating the BIOS configuration setting and transmitting a response instruction to the remote computer.

Abstract: In an embodiment, a method includes forming a plurality of semiconductor fins over a substrate, the plurality of semiconductor fins comprising a first fin, a second fin, a third fin, and a fourth fin; forming a first dielectric layer over the plurality of semiconductor fins, the first dielectric layer filling an entirety of a first trench between the first fin and the second fin; forming a second dielectric layer over the first dielectric layer, the second dielectric layer filling an entirety of a second trench between the second fin and the third fin, the forming the second dielectric layer comprising: forming an oxynitride layer; and forming an oxide layer; and forming a third dielectric layer over the second dielectric layer, the third dielectric layer filling an entirety of a third trench between the third fin and the fourth fin.

Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.

Abstract: A MEMS die includes a substrate having an opening formed therein, and a diaphragm attached around a periphery thereof to the substrate and over the opening, wherein the diaphragm comprises first and second spaced apart layers. A backplate is disposed between the first and second spaced apart layers. One or more columnar supports are disposed through holes disposed through the backplate and connecting the first and second spaced apart layers. At least a partial vacuum exists between at least a portion of the first and second spaced apart layers. The first layer further comprises interior and exterior sub-layers at least proximate to each of the one or more columnar supports, wherein the interior sub-layers include one or more apertures disposed therethrough.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.

Abstract: The present disclosure provides an engineered stem cell, comprising a vector comprising a polynucleotide comprising a nucleic acid sequence of suicide gene, a nucleic acid sequence of immune checkpoint gene and a natural cytotoxicity triggering receptor or a TNF-related apoptosis-inducing ligand, wherein the stem cell is a tumor-targeting cell. The present disclosure also provides a method for treating a cancer or enhancing intratumor immunity or enhancing immunity in tumor microenvironment in a subject, comprising administering an effective amount of the engineered stem cell of the present disclosure to the subject.

Abstract: A para-aortic blood pump device includes a blood pump, an aortic adapter, a driveline, and a driver. The blood pump includes a blood sac, a pump housing and a pressure sensor, whereas the pressure sensor is installed in the pump housing for monitoring the blood pressure inside the blood pump. The aortic adapter is a T-manifold shaped conduit connected to the blood pump and is used for connecting the blood pump with human aorta to facilitate circulatory support. The driveline allows a pneumatic communication to the blood pump in addition to transmitting the electrical blood pressure signal to the driver. The driver receives and processes the electrical blood pressure signal, decides the timing, speed and duration of blood pump fill and eject actions so as to provide counter-pulsatile circulatory support to assist human circulation.

Abstract: The present disclosure provides a structure and a method to reduce electro-migration. An interconnect structure according to the present disclosure includes a conductive feature embedded in a dielectric layer, a capping barrier layer disposed over the conductive feature and the dielectric layer, and an adhesion layer sandwiched between the capping barrier layer and the dielectric layer. The adhesion layer includes a degree of crystallinity between about 40% and about 70%.

Abstract: A wafer stage includes an area for receiving a wafer. The wafer stage further includes a first sensor outside of the area for receiving the wafer. The wafer stage further includes a second sensor outside of the area of receiving the wafer, wherein the second sensor is spaced from the first sensor. The wafer stage further includes a first particle capture area outside of the area for receiving the wafer, wherein the first particle capture area is spaced from both the first sensor and the second sensor, a dimension of the first particle capture area in a first direction parallel to a top surface of the wafer stage is at least 26 millimeters (mm), a dimension of the first particle capture area in a second direction parallel to the top surface of the wafer stage is at least 33 mm, and the second direction is perpendicular to the first direction.

Abstract: A Quality of Experience (QoE) optimization system and method are provided. An electronic device inputs key performance indicators (KPIs) and system control parameters collected from a core network, a base station and a user equipment (UE) into a QoE optimization model. The QoE optimization model then optimizes the system control parameters based on the KPIs and a user QoE fed back from the UE to output optimized system control parameters. Furthermore, a strategy emulator controls at least one of a base station emulator and a UE emulator, so as to emulate the QoE optimization model using the at least one of the base station emulator and the UE emulator. Non-real-time optimization adjustments to the QoE optimization model are made based on the result of the emulation performed by the at least one of the base station emulator and the UE emulator.

Abstract: The invention discloses a novel vascular punch employing compressive normal force for tissue separation from a targeted vessel. This invention is particularly designed for making a large round hole without massive bleeding in vascular surgery. A clean, non-frayed hole-making guided by the normal force cutting principle is realized using a site-biting punch mechanism. The side-biting vascular punch comprises a U-shaped razor blade cutter, a backstop for receiving the cutter, and a linkage mechanism, forming an aligned line of contact for normal compression force generation and thereby severing tissue out of the targeted vessel.

Abstract: Network side beacon reports (NSBRs) may be generated based on probe signals received from one or more client devices (CDs) in a wireless network. Once enabled, an NSBR mode is configured to generate NSBRs remotely from a CD. When in the NSBR mode, an NSBR may be generated based on compiled probe signal parameters associated with one or more probe signals received from the CD.

Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Abstract: A touch control light adjustable device including a first transparent substrate, a macromolecule dispersed liquid crystal composite layer, a first touch control structure, and a driving circuit is provided. The first transparent substrate has a first surface and a second surface opposite to each other. The macromolecule dispersed liquid crystal composite layer is disposed on the first surface of the first transparent substrate. The first touch control structure is disposed on the second surface of the first transparent substrate. The macromolecule dispersed liquid crystal composite layer and the first touch control structure are electrically connected to the driving circuit. The driving circuit provides a voltage signal to drive the macromolecule dispersed liquid crystal composite layer based on a change of a capacitance value of at least one capacitor in the driving circuit by touching the surface of the first touch control structure.