Patents by Inventor Chien-Ming Lai

Chien-Ming Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220244499
    Abstract: A six-piece optical image capturing system is disclosed. In order from an object side to an image side, the optical lenses along the optical axis include a first lens with refractive power; a second lens with refractive power; a third lens with refractive power; a fourth lens with refractive power; a fifth lens with refractive power, and a sixth lens with negative refractive power. At least one lens among the first lens to the fifth lens has positive refractive power. The image-side surface and object-side surface of the sixth lens are aspheric, and at least one of the image-side surface and the object-side surface of the sixth lens has an inflection point. The optical lens of the optical image capturing system can increase aperture value and improve the imagining quality for use in compact cameras.
    Type: Application
    Filed: June 24, 2021
    Publication date: August 4, 2022
    Inventors: Yeong-Ming Chang, Chien-Hsun Lai, Yao-Wei Liu
  • Patent number: 11402612
    Abstract: An optical image capturing system includes, along the optical axis in order from an object side to an image side, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens, and a seventh lens. At least one lens among the first to the sixth lenses has positive refractive force. The seventh lens can have negative refractive force, wherein both the surfaces of the seventh lens are aspheric surfaces, and at least one surface of the seventh lens has an inflection point. The lenses in the optical image capturing system which have refractive power include the first to the seventh lenses. The optical image capturing system can increase aperture value and improve the imaging quality for use in compact cameras.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 2, 2022
    Assignee: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yeong-Ming Chang, Chien-Hsun Lai, Yao-Wei Liu
  • Publication number: 20220236531
    Abstract: A six-piece optical image capturing system is disclosed. In order from an object side to an image side, the optical lens along the optical axis includes a first lens with refractive power; a second lens with refractive power; a third lens with refractive power; a fourth lens with refractive power; a fifth lens with refractive power, and a sixth lens with negative refractive power. The image-side surface and object-side surface of the sixth lens are aspheric, and at least one surface of the sixth lens has an inflection point. At least one among the first lens to the fifth lens has positive refractive power. The optical lens of the optical image capturing system can increase aperture value and improve the imagining quality for use in compact cameras.
    Type: Application
    Filed: June 24, 2021
    Publication date: July 28, 2022
    Inventors: Yeong-Ming Chang, Chien-Hsun Lai, Yao-Wei Liu
  • Patent number: 11397310
    Abstract: A four-piece optical image capturing system is disclosed. In order from an object side to an image side, the optical image capturing system along the optical axis includes a first lens with positive refractive power; a second lens with refractive power; a third lens with refractive power; and a fourth lens with refractive power; and at least one of the image-side surface and object-side surface of each of the four lenses are aspheric. The optical image capturing system can increase aperture value and improve the imagining quality for use in compact cameras.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: July 26, 2022
    Assignee: Ability Opto-Electronics Technology Co., Ltd.
    Inventors: Yeong-Ming Chang, Chien-Hsun Lai, Yao-Wei Liu
  • Publication number: 20220223591
    Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 14, 2022
    Inventors: Yen-Ting Chen, Bo-Yu Lai, Chien-Wei Lee, Hsueh-Chang Sung, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11387408
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: July 12, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Publication number: 20220200018
    Abstract: An air-cooling fuel cell stack includes fuel cells, wherein each of the fuel cells includes an anode bipolar plate, a cathode bipolar plate, a membrane electrode assembly (MEA) between the anode and cathode bipolar plates, and an anode sealing member. The MEA includes an anode side structure, a cathode side structure, and an ion conductive membrane (ICM), and the ICM is sandwiched between the anode side structure and the cathode side structure. The anode sealing member is disposed at a periphery of the anode side structure and sandwiched by the anode bipolar plate and the ICM. The anode sealing member includes a first sealing material and a second sealing material, a Shore hardness of the first sealing material is different from that of the second sealing material, and an arrangement direction of the first and second sealing materials is perpendicular to a compression direction of the plurality of fuel cells.
    Type: Application
    Filed: October 8, 2021
    Publication date: June 23, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Sung-Chun Chang, Chien-Ming Lai, Chiu-Ping Huang, Keng-Yang Chen, Li-Duan Tsai
  • Publication number: 20220189888
    Abstract: A semiconductor structure in which the upper and lower semiconductor wafers are bonded by a hybrid bonding method is provided. The two semiconductor wafers each have discontinuous multiple metal traces or spiral coil-shaped metal traces. By hybrid bonding the two semiconductor wafers, multiple discontinuous metal traces are bonded together to form an inductance element with a continuous and non-intersecting path, or the two spiral coil-shaped metal traces are bonded together to form an inductance element. In this semiconductor structure, the inductance element formed by hybrid bonding has the advantage that the inductance value is easily adjusted.
    Type: Application
    Filed: January 27, 2021
    Publication date: June 16, 2022
    Inventors: Chien-Ming Lai, Hui-Ling Chen, Zhi-Rui Sheng
  • Patent number: 11355431
    Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: June 7, 2022
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chien-Ming Lai, Zhi-Rui Sheng, Hui-Ling Chen
  • Patent number: 11342465
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Grant
    Filed: January 3, 2021
    Date of Patent: May 24, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Publication number: 20220108946
    Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.
    Type: Application
    Filed: October 7, 2020
    Publication date: April 7, 2022
    Inventors: Chien-Ming Lai, Zhi-Rui Sheng, Hui-Ling Chen
  • Patent number: 11164822
    Abstract: A structure of semiconductor device is provided. The structure includes a first bonding pattern, formed on a first substrate. A first grating pattern is disposed on the first substrate, having a plurality of first bars extending along a first direction. A second bonding pattern is formed on a second substrate. A second grating pattern, disposed on the second substrate, having a plurality of second bars extending along the first direction. The first bonding pattern is bonded to the second bonding pattern. One of the first grating pattern and the second grating pattern is stacked over and overlapping at the first direction with another one of the first grating pattern and the second grating pattern. A first gap between adjacent two of the first bars is different from a second gap between adjacent two of the second bars.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: November 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Hui-Ling Chen, Chien-Ming Lai
  • Publication number: 20210336059
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 28, 2021
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Patent number: 11145867
    Abstract: Surface-treated copper foils exhibiting a void volume (Vv) in a range of 0.4 to 2.2 ?m3/?m2 and an arithmetic mean waviness (Wa) lower than or equal to 0.4 ?m are reported. Where the surface-treated copper foil is treated on the drum side and includes a treatment layer comprising a nodule layer. Such surface-treated copper foils can be used as a conductive material having low transmission loss, for example in circuit boards.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: October 12, 2021
    Assignee: CHANG CHUN PETROCHEMICAL CO., LTD.
    Inventors: Chien-Ming Lai, Yao-Sheng Lai, Jui-Chang Chou
  • Patent number: 11088285
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: August 10, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Publication number: 20210126131
    Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.
    Type: Application
    Filed: January 3, 2021
    Publication date: April 29, 2021
    Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
  • Patent number: 10923730
    Abstract: Electrodeposited copper foils possessing properties for manufacturing lithium ion rechargeable secondary batteries are described, including methods of making the electrodeposited copper foils, methods for making the battery, and the resultant battery. The electrodeposited copper foils have a specific burst strength in the range of 1.5 to 4.3 kPa*m2/g and a tensile strength in the range of 30 to 40 kgf/mm2. The deposited side of the electrodeposited copper foil has a surface hardness in the range of 0.2 to about 2.0 Gpa by nano indentation analysis to resist wrinkling during pressing of the active materials on the electrodeposited copper foil. The foil exhibits reduced copper burr formation and burr size after clipping.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: February 16, 2021
    Assignee: CHANG CHUN PETROCHEMICAL CO., LTD.
    Inventors: Yao-Sheng Lai, Kuei-Sen Cheng, Jui-Chang Chou, Chien-Ming Lai
  • Publication number: 20200295378
    Abstract: Electrodeposited copper foils possessing properties for manufacturing lithium ion rechargeable secondary batteries are described, including methods of making the electrodeposited copper foils, methods for making the battery, and the resultant battery. The electrodeposited copper foils have a specific burst strength in the range of 1.5 to 4.3 kPa*m2/g and a tensile strength in the range of 30 to 40 kgf/mm2. The deposited side of the electrodeposited copper foil has a surface hardness in the range of 0.2 to about 2.0 Gpa by nano indentation analysis to resist wrinkling during pressing of the active materials on the electrodeposited copper foil. The foil exhibits reduced copper burr formation and burr size after clipping.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Inventors: Yao-Sheng LAI, Kuei-Sen CHENG, Jui-Chang CHOU, Chien-Ming LAI
  • Patent number: 10772199
    Abstract: Surface-treated copper foils that exhibit a material volume (Vm) less than 1.90 ?m3/?m2. Where the surface-treated copper foil is treated on the drum side and includes a treatment layer comprising a nodule layer. Such surface-treated copper foils can be used as a conductive material having low transmission loss, for example in circuit boards.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 8, 2020
    Assignee: CHANG CHUN PETROCHEMICAL CO., LTD.
    Inventors: Chien-Ming Lai, Yao-Sheng Lai, Jui-Chang Chou
  • Patent number: D958711
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: July 26, 2022
    Assignee: ABILITY OPTO-ELECTRONICS TECHNOLOGY CO. LTD.
    Inventors: Yeong-Ming Chang, Yi-Chi Cheng, Tzu-Hsuan Wei, Chien-Hsun Lai, Yao-Wei Liu