Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.

Abstract: A metal gate transistor is disclosed. The metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate. The metal gate further includes a high-k dielectric layer, a bottom barrier metal (BBM) layer on the high-k dielectric layer, a first work function layer on the BBM layer, a second work function layer between the BBM layer and the first work function layer, and a low resistance metal layer on the first work function layer. Preferably, the first work function layer includes a p-type work function layer and the second work function layer includes a n-type work function layer.

Abstract: A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.

Abstract: A semiconductor device having metal gate includes a substrate, a first metal gate positioned on the substrate, and a second metal gate positioned on the substrate. The first metal gate includes a first p-work function metal layer, an n-work function metal layer, and a gap-filling metal layer. The second metal gate includes a second p-work function metal layer, the n-work function metal layer, and the gap-filling metal layer. The first p-work function metal layer and the second p-work function metal layer include a same p-typed metal material. A thickness of the first p-work function metal layer is larger than a thickness of the second p-work function metal layer. The first p-work function metal layer, the second p-work function metal layer, and the n-work function metal layer include a U shape.

Abstract: A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.

Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.

Abstract: A wireless signal access apparatus receives wireless signals of IEEE 802.11 standard for controlling at least one appliance. The appliance may receive control signals of IEEE 802.15 standard, to be controlled according to the control signals. The wireless signal access apparatus receives the wireless signals having control data to generate the control signal of IEEE 802.15 standard, and send it to the appliance for omnidirectional remote control of the appliance.

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

Abstract: A manufacturing method for a semiconductor device having a metal gate is provided. First and second gate trenches are respectively formed in first and second semiconductor devices. A work-function metal layer is formed in the first and second gate trenches. A shielding layer is formed on the substrate. A first removing step is performed, so that the remaining shielding layer is at bottom of the second gate trench and fills up the first gate trench. A second removing step is performed, so that the remaining shielding layer is at bottom of the first gate trench to expose the work-function metal layer at sidewall of the first gate trench and in the second gate trench. The work-function metal layer not covered by the remaining shielding layer is removed, so that the remaining work-function metal layer is only at bottom of the first gate trench. The remaining shielding layer is removed.

Abstract: A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side of one layer of the multi-layered stack structure closer to the gate dielectric layer is less than that in the side of one layer of the multi-layered stack structure opposite to the gate dielectric layer.

Abstract: A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.

Abstract: A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer.

Abstract: An organic/inorganic hybrid composite proton exchange membrane is provided. The proton exchange membrane includes an inorganic material of about 0.5-30 parts by weight and an organic material of about 99.5-70 parts by weight per 100 parts by weight of the proton exchange membrane. A surface area of the inorganic material is about 50-3000 m2/g. The organic material includes a sulfonated polymer or a phosphoric acid doped polymer.