Abstract: An air-cooling fuel cell stack includes fuel cells, wherein each of the fuel cells includes an anode bipolar plate, a cathode bipolar plate, a membrane electrode assembly (MEA) between the anode and cathode bipolar plates, and an anode sealing member. The MEA includes an anode side structure, a cathode side structure, and an ion conductive membrane (ICM), and the ICM is sandwiched between the anode side structure and the cathode side structure. The anode sealing member is disposed at a periphery of the anode side structure and sandwiched by the anode bipolar plate and the ICM. The anode sealing member includes a first sealing material and a second sealing material, a Shore hardness of the first sealing material is different from that of the second sealing material, and an arrangement direction of the first and second sealing materials is perpendicular to a compression direction of the plurality of fuel cells.

Abstract: A semiconductor structure in which the upper and lower semiconductor wafers are bonded by a hybrid bonding method is provided. The two semiconductor wafers each have discontinuous multiple metal traces or spiral coil-shaped metal traces. By hybrid bonding the two semiconductor wafers, multiple discontinuous metal traces are bonded together to form an inductance element with a continuous and non-intersecting path, or the two spiral coil-shaped metal traces are bonded together to form an inductance element. In this semiconductor structure, the inductance element formed by hybrid bonding has the advantage that the inductance value is easily adjusted.

Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: A semiconductor structure includes a first layer, a second layer, a first interconnection layer, and a second interconnection layer. The first layer includes an upper electrode pattern, and the second layer includes a lower electrode pattern, wherein the upper electrode pattern is opposite to the lower electrode pattern. The first interconnection layer includes a plurality of first interconnect structures electrically connected on the upper electrode pattern. The second interconnection layer includes a plurality of second interconnect structures electrically connected on the lower electrode pattern. The first interconnect structures on the upper electrode pattern are hybrid bonded with the second interconnect structures on the lower electrode pattern. Therefore, the upper electrode patterns and the lower electrode patterns are joined by hybrid bonding to form a capacitor element.

Abstract: A structure of semiconductor device is provided. The structure includes a first bonding pattern, formed on a first substrate. A first grating pattern is disposed on the first substrate, having a plurality of first bars extending along a first direction. A second bonding pattern is formed on a second substrate. A second grating pattern, disposed on the second substrate, having a plurality of second bars extending along the first direction. The first bonding pattern is bonded to the second bonding pattern. One of the first grating pattern and the second grating pattern is stacked over and overlapping at the first direction with another one of the first grating pattern and the second grating pattern. A first gap between adjacent two of the first bars is different from a second gap between adjacent two of the second bars.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: Surface-treated copper foils exhibiting a void volume (Vv) in a range of 0.4 to 2.2 ?m3/?m2 and an arithmetic mean waviness (Wa) lower than or equal to 0.4 ?m are reported. Where the surface-treated copper foil is treated on the drum side and includes a treatment layer comprising a nodule layer. Such surface-treated copper foils can be used as a conductive material having low transmission loss, for example in circuit boards.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: Electrodeposited copper foils possessing properties for manufacturing lithium ion rechargeable secondary batteries are described, including methods of making the electrodeposited copper foils, methods for making the battery, and the resultant battery. The electrodeposited copper foils have a specific burst strength in the range of 1.5 to 4.3 kPa*m2/g and a tensile strength in the range of 30 to 40 kgf/mm2. The deposited side of the electrodeposited copper foil has a surface hardness in the range of 0.2 to about 2.0 Gpa by nano indentation analysis to resist wrinkling during pressing of the active materials on the electrodeposited copper foil. The foil exhibits reduced copper burr formation and burr size after clipping.

Abstract: Electrodeposited copper foils possessing properties for manufacturing lithium ion rechargeable secondary batteries are described, including methods of making the electrodeposited copper foils, methods for making the battery, and the resultant battery. The electrodeposited copper foils have a specific burst strength in the range of 1.5 to 4.3 kPa*m2/g and a tensile strength in the range of 30 to 40 kgf/mm2. The deposited side of the electrodeposited copper foil has a surface hardness in the range of 0.2 to about 2.0 Gpa by nano indentation analysis to resist wrinkling during pressing of the active materials on the electrodeposited copper foil. The foil exhibits reduced copper burr formation and burr size after clipping.

Abstract: Surface-treated copper foils that exhibit a material volume (Vm) less than 1.90 ?m3/?m2. Where the surface-treated copper foil is treated on the drum side and includes a treatment layer comprising a nodule layer. Such surface-treated copper foils can be used as a conductive material having low transmission loss, for example in circuit boards.

Abstract: Surface-treated copper foils that exhibit a material volume (Vm) less than 1.90 ?m3/?m2. Where the surface-treated copper foil is treated on the drum side and includes a treatment layer comprising a nodule layer. Such surface-treated copper foils can be used as a conductive material having low transmission loss, for example in circuit boards.

Abstract: Surface-treated copper foils exhibiting a void volume (Vv) in a range of 0.4 to 2.2 ?m3/?m2 and an arithmetic mean waviness (Wa) lower than or equal to 0.4 ?m are reported. Where the surface-treated copper foil is treated on the drum side and includes a treatment layer comprising a nodule layer. Such surface-treated copper foils can be used as a conductive material having low transmission loss, for example in circuit boards.

Abstract: Provided is an electrolytic copper foil. The electrolytic copper foil has a drum side and a deposited side, wherein ?Rz is less than 0.8 ?m; the electrolytic copper foil has a transverse direction, wherein the electrolytic copper foil is divided into 10 test pieces with the same width and the same length, and each two adjacent ones of the 10 test pieces have a weight deviation therebetween, and a count of the weight deviation(s) greater than or equal to 1.5% is smaller than a count of the weight deviations smaller than 1.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: An electrocatalyst is provided. The electrocatalyst includes Pd-containing metal nitride, wherein the metal is Co, Fe, Y, Lu, Sc, Ti, V, Cu, Ni, or a combination thereof. The molar ratio between the metal and Pd is greater than 0 and less than or equal to 0.8. A fuel cell utilizing the above electrocatalyst is further provided.

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.