Abstract: A magneto-resistive random access memory with segmented bottom electrode includes a magnetic tunnel junction pillar above a first portion of a bottom electrode layer, the first portion of the bottom electrode layer includes a metal region. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar and above a second portion of the bottom electrode layer including a metal-oxide region. The first portion of the bottom electrode layer composed of the metal region and the second portion of the bottom electrode layer composed of the metal-oxide region form the segmented bottom electrode.

Abstract: An electrical fuse for an integrated circuit (IC). The electrical fuse includes a dielectric material substrate, and at least one line of conducting material located in the dielectric material substrate. Each of the at least one line of conducting material includes a first conductive structure, a second conductive structure, and a fuse element extending horizontally between the first and second conductive structures. The fuse element has a height that is less than the height of the first and second conductive structures.

Abstract: A back-end-of-the-line (BEOL) interconnect structure is provided that includes a top via structure located on a metal line. An air gap is located adjacent to, and around, the metal line and top via structure. This air gap includes a lower portion adjacent to the metal line and an upper portion adjacent to the top via structure. Such an air gap can extend BEOL interconnect scaling for 2 nm technology node and below. Methods of forming such an BEOL interconnect structure are also provided.

Abstract: A magnetoresistive random access memory (MRAM) includes a pillar structure having a bottom electrode and a magnetic tunnel junction (MTJ) having a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer. The MTJ is disposed on the bottom electrode. A top electrode is disposed on the MTJ. The top electrode includes two or more tiers wherein each tier successively includes a smaller footprint.

Abstract: A metal-insulator-metal (MIM) capacitor includes a dielectric layer forming a plane and a capacitor dielectric formed in a pattern having a width parallel to the plane and a height transverse to the plane. Electrodes are formed as sidewall spacers on opposite sides of the width of the capacitor dielectric. Each of the electrodes has a contact to make an electrical connection to the electrode, the contact being disposed within the height.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A metal line is formed on a bottom liner, a sacrificial hardmask on a top surface of the metal line. Portions of the sacrificial hardmask are selectively removed that that do not correspond a desired location of a top via. The remaining sacrificial hardmask is replaced with the top via, the top via and the metal line each tapered such that a width at each respective bottom surface is greater than a width of each respective top surface.

Abstract: Aspects of the present invention provide a three-dimensional resistor with at least two horizontal resistive metal elements connected by at least one vertical resistive metal element. Each of the vertical resistive metal elements surrounds a portion of a first dielectric material where the portion of resistive metal surrounding the dielectric material forms a tube of the resistive metal. More than one vertical resistive metal element with a thickness between one and five nanometers can be present between each of two adjacent horizontal resistive metal elements.

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack. A semiconductor device is provided. The semiconductor device including a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack, where the tunneling barrier comprises a center portion and two outer portions, where the center portion is on an upper horizontal portion of the reference layer, and the two outer portions are on a slanted upper surface of an encapsulation layer surrounding the reference layer. Forming a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack.

Abstract: A antifuse structure including a first metal sidewall spacer and a second metal sidewall spacer arranged on opposite sides of a tapered dielectric pedestal, and a fuse dielectric on top of the tapered dielectric pedestal and between the first metal sidewall spacer and the second metal sidewall spacer.

Abstract: A semiconductor structure including a metal sidewall spacer arranged on a vertical sidewall of a dielectric pedestal, a fuse dielectric layer on top of the dielectric pedestal, and a conductive element on top of the fuse dielectric layer and directly above the metal sidewall spacer.

Abstract: A semiconductor device including a first stacked nanosheet Field Effect Transistor (FET), a second stacked nanosheet, a metal insulator metal (MIM) capacitor between the first stacked nanosheet and the second stacked nanosheet and an insulator separating the MIM capacitor from each of the first stacked nanosheet and the second stacked nanosheet. An embodiment where the first stacked nanosheet and the second stacked nanosheet each include an upper stacked nanosheet and a lower stacked nanosheet, the upper stacked nanosheet and the lower stacked nanosheet each include alternating layers of a sacrificial material and a semiconductor channel material vertically aligned and stacked one on top of another. Forming a first stacked nanosheet, forming a second stacked nanosheet, forming a MIM capacitor between the first stacked nanosheet and the second stacked nanosheet and forming an insulator separating the MIM capacitor from each of the first stacked nanosheet and the second stacked nanosheet.

Abstract: A horizontal antifuse structure including a fuse dielectric layer, two slanted annular metal structures arranged adjacent to and opposite one another, wherein bottom portions of the two slanted annular metal structures are embedded in the fuse dielectric layer.

Abstract: An antifuse structure including a first fuse conductor, a second fuse conductor in the same metallization level as the second fuse conductor, and a tapered fuse dielectric between and separating the first fuse conductor from the second fuse conductor.

Abstract: A structure that includes a plurality of circular metal elements that are concentrically arranged and connected through a plurality of metal connectors, wherein the structure forms a circular resistor.

Abstract: A semiconductor device includes a first metallization level comprising a first electrode and a second metallization level comprising a second electrode. A resistor structure is disposed between the first electrode and the second electrode. The resistor structure comprises a first resistor element comprising a first side and a second side, wherein the first side has a larger area than an area of the second side, and a second resistor element stacked on the first resistor element, wherein the second resistor element contacts the second side of the first resistor element.

Abstract: A magnetic tunnel junction pillar is positioned above a bottom electrode composed of a metal-oxide region in contact with a first portion of the magnetic tunnel junction pillar and a metal region surrounding the metal-oxide region. A sidewall spacer is positioned along sidewalls of the magnetic tunnel junction pillar, and the metal region is in contact with a bottom surface of the sidewall spacer and a second portion of the magnetic tunnel junction pillar.

Abstract: A fuse structure including a first conductive line and a second conductive line, a first metal pillar extending vertically from a top surface of the first conductive line and a second metal pillar extending vertically from a top surface of the second conductive line, a conductive link electrically connecting a top surface of the first metal pillar with a top surface of the second metal pillar, where both the first conductive line and the second conductive line are a different material than both the first metal pillar and the second metal pillar, and where both the first metal pillar and the second metal pillar are a different metal than the conductive link.

Abstract: A BIOS setup environment configuration modification audit system includes a BIOS device that is included in a computing device and that is coupled to a component device in the computing device. The BIOS device enters a BIOS setup environment for the computing device and, while in the BIOS setup environment, detects component device configuration modification(s) to a configuration of the component device.

Abstract: A semiconductor device includes a dual layer top contact upon a MTJ stack. The dual layer top contact includes lower contact and upper contact. The lower contact may be wider and/or shallower relative to the upper contact. This wide and/or shallow geometry of the lower contact may decrease the propensity for over etching, during the formation of the upper contact, opening downward into the MTJ stack and may therefore prevent undesired shorting of the MTJ stack. Further, the lower contact may further protect the MTJ stack even when the upper contact is misaligned to the MTJ stack.

Abstract: An interconnect structure includes a first via metallization layer having at least a first metal via, a second via metallization layer having at least a second metal via, and a first metallization layer disposed between the first via metallization layer and the second via metallization layer, the first metallization layer comprising a first metal line and a second metal line. The first metal via is disposed on the first metal line and the second metal via is disposed on the second metal line. The second metal via is in an overlapping configuration with the first metal via.