Abstract: A magnetoresistive random access memory (MRAM) includes a pillar structure having a bottom electrode, a magnetic tunnel junction (MTJ) and a top electrode disposed on the MTJ. The MTJ has a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer. The MTJ is disposed on the bottom electrode. The bottom electrode and the top electrode are recessed within a periphery of the MTJ to form a disrupted sidewall profile.

Abstract: A semiconductor device includes a metal-insulator-metal capacitor disposed between a first metallization level and a second metallization level, the metal-insulator-metal capacitor comprising a first electrode, a second electrode and a third electrode. A first via is extended from and contacts a conductive line of the second metallization level, and a second via is extended from and contacts the first via. The second via contacts the first electrode and the third electrode of the metal-insulator-metal capacitor. A slope of a side surface of the first via is different from a slope of a side surface of the second via.

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack and an upper word line of the MTJ stack surrounding vertical side surfaces of the MTJ stack. A semiconductor device including a magnetic tunnel junction (MTJ) stack and an upper word line for the MTJ stack surrounding vertical side surfaces and an upper surface of a reference layer of the MTJ stack. A method including forming a forming a magnetic tunnel junction (MTJ) stack and forming a dielectric encapsulation layer surrounding vertical side surfaces of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode of the MTJ stack.

Abstract: A magnetoresistive random access memory (MRAM) includes a first conductor and a magnetic tunnel junction (MTJ) having a bottom electrode. An anchor via connects the first conductor to the bottom electrode. The anchor via includes a via conductor encapsulated within a diffusion barrier. The diffusion barrier includes a conductive cap disposed between the via conductor and the bottom electrode.

Abstract: A semiconductor device includes a metal line having a longitudinal axis. The metal line includes a first segment extending in a direction of the longitudinal axis and having a first cross-section, the first cross-section including a wider side and a narrower side. A second segment extends in a direction of the longitudinal axis and has a second cross-section, the second cross-section including a wider side and a narrower side. The narrower side of the second segment is formed in contact with the wider side of the first segment such that a portion of the wider side of the first segment extends beyond the narrow side of the second segment to form a terrace and the terrace and a tapered sidewall of the second segment form an acute angle.

Abstract: A semiconductor substrate has a metal via in the substrate, and has, on the substrate, a metal line that is less than 8 nanometers (nm) wide and at least 20 nm tall. A method for making a semiconductor structure includes forming a metal via in a substrate; forming a mandrel atop and offset from the via; depositing a metal-containing liner onto the mandrel; exposing the top of the mandrel by anisotropically etching the liner, thereby defining a separate portion of the liner at each side of the mandrel; and growing a metal line on each portion of the liner.

Abstract: A metal insulator metal capacitor (MIM capacitor) between adjacent stacked nanosheet FETs, each include a first nanosheet stack including alternating layers of a first work function metal and a semiconductor channel material vertically aligned and stacked one on top of another and a second nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material vertically aligned and stacked one on top of another, the second nanosheet stack on the first nanosheet stack. Forming adjacent stacked nanosheet FETs, each include a first nanosheet stack and a second nanosheet stack, the second nanosheet stack on the first nanosheet stack, and forming a MIM capacitor between adjacent stacked nanosheet field effect transistors.

Abstract: According to the embodiment of the present invention, a semiconductor device includes an interconnect. The interconnect includes a bottom interconnect section and a top interconnect section. The bottom interconnect section includes a first orientation along a Y-axis. The top interconnect section is coupled to the bottom interconnect section and includes a second orientation along to the Y-axis. The second orientation of the top interconnect section is a vertical reflection of the first orientation of the bottom interconnect section.

Abstract: A semiconductor device including a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry, where a bottom electrode of the MIM capacitor includes a plurality of vertical pillars extending up from a bottom layer. A semiconductor device including a metal insulator metal capacitor (MIM capacitor), where a bottom electrode of the MIM capacitor includes a plurality of vertical pillars extending up from a bottom layer. Forming back end of line Mx-1 metal line layer, forming a plurality of Vx-1 via on the Mx-1 metal line layer, forming Mx metal line layer with subtractive patterning on the plurality of the Vx-1 via, forming a plurality of Vx via on the Mx metal line layer with subtractive patterning; and forming a block mask protecting a portion of the semiconductor device.

Abstract: A semiconductor device including a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry of the semiconductor device, where the MIM capacitor surrounds a first Mx metal line. A semiconductor device including a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry of the semiconductor device, where the MIM capacitor surrounds a first Mx metal line, where a lower horizontal surface of the MIM capacitor is vertically adjacent to an upper horizontal surface of an Mx-1 metal line. A method including forming a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry of the semiconductor device, where the MIM capacitor surrounds a first Mx metal line.

Abstract: Memory structures including an MTJ-containing pillar that is void of re-sputtered bottom electrode metal particles is provided by first forming the MTJ-containing pillar on a sacrificial material-containing structure, and thereafter replacing the sacrificial material-containing structure with at least a replacement bottom electrode structure. In some embodiments, the sacrificial material-containing structure is replaced with both a bottom electrode diffusion barrier liner and a replacement bottom electrode structure.

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a cross section of a bottom electrode of the MTJ stack comprises a trapezoid profile. A semiconductor device including a lower word line and a first electrode above and connected to the lower word line, where a cross section of an electrode includes a trapezoid profile. A method including forming a bottom electrode, the bottom electrode includes a tapered side surface including a width at an upper surface of the bottom electrode less than a width at a lower surface of the bottom electrode.

Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a cross section of a bottom electrode of the stack includes a hexagonal profile. A semiconductor device including a lower word line, a magnetic tunnel junction (MTJ) stack, where a cross section of a first electrode of the MTJ stack comprises a hexagonal profile. A method including forming a bottom electrode, the bottom electrode includes a side surface including a width at a middle section of the bottom electrode greater than a width at a lower surface of the bottom electrode, and the width at the middle section of the bottom electrode greater than a width at an upper surface of the bottom electrode.

Abstract: A semiconductor device, such as an MRAM device, includes a stepped contact within a memory region that has a greater number of different contact structures (i.e., contact structures formed in different fabrication stages) relative to a logic region contact. The stepped contact includes a lower stepped contact and an upper stepped contact. The inclusion of the lower stepped contact allows for a relatively shorter upper stepped contact compared to the logic region contact. The stepped contact may allow the use of a multi-layer encapsulation spacer upon the sidewalls of a memory cell that fill out tight spacing therebetween, which may decrease the propensity of void formation and resulting shorting between neighboring memory cell features.

Abstract: A semiconductor structure that includes a metal level, a via located directly on top of a first portion of the metal level, wherein the via is tapered such that a smaller critical dimension is located at a top portion of the via and a larger critical dimension is located at a bottom portion of the via, and the bottom portion of the via is located adjacent the metal level, a dielectric cap located on top of a second portion of the metal level on which the via is not located directly thereon, and a next metal level that is located directly on the top portion of the via.

Abstract: A semiconductor structure comprises a memory device comprising a first electrode, at least one memory element layer disposed on the first electrode, and a second electrode disposed on the at least one memory element layer. An encapsulation layer is disposed around side surfaces of the memory device. The semiconductor structure also comprises a conductive cap layer disposed on a top surface of the encapsulation layer and around a portion of side surfaces of the encapsulation layer. A contact is disposed on the second electrode and extends around the side surfaces of the memory device.

Abstract: A semiconductor structure comprises a bottom electrode contact, and a memory device comprising a bottom electrode disposed on the bottom electrode contact, at least one memory element layer disposed on the bottom electrode, and a top electrode disposed on the at least one memory element layer. A bit line contact is disposed on the top electrode and extends around sides of the memory device and of the bottom electrode contact. An encapsulation layer is disposed between the bit line contact and the sides of the memory device and of the bottom electrode contact.

Abstract: A semiconductor structure including a homogeneous interconnect structure embedded in a dielectric layer, where the homogeneous interconnect structure includes a third region vertically aligned above a second region vertically aligned above a first region, the third region includes three sections: an upper section including a first width; a middle section including an upper horizontal surface including the first width and a lower horizontal surface including a second width; and a lower section including the second width; where the first width is less than the second width; and the second region including a third width at an upper horizontal surface of the second region and a fourth width at a lower horizontal surface of the second region, where the third width is greater than the fourth width.

Abstract: A semiconductor structure comprises a reference layer of a magnetic random-access memory pillar structure, the reference layer having a first diameter, a free layer of the magnetic random-access memory pillar structure disposed over the reference layer, the free layer having a second diameter, and an electrode layer of the magnetic random-access memory pillar structure disposed over the free layer, the electrode layer having a third diameter. At least two of the first diameter, the second diameter and the third diameter are different.