Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a cross section of a bottom electrode of the MTJ stack comprises a trapezoid profile. A semiconductor device including a lower word line and a first electrode above and connected to the lower word line, where a cross section of an electrode includes a trapezoid profile. A method including forming a bottom electrode, the bottom electrode includes a tapered side surface including a width at an upper surface of the bottom electrode less than a width at a lower surface of the bottom electrode.

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a cross section of a bottom electrode of the stack includes a hexagonal profile. A semiconductor device including a lower word line, a magnetic tunnel junction (MTJ) stack, where a cross section of a first electrode of the MTJ stack comprises a hexagonal profile. A method including forming a bottom electrode, the bottom electrode includes a side surface including a width at a middle section of the bottom electrode greater than a width at a lower surface of the bottom electrode, and the width at the middle section of the bottom electrode greater than a width at an upper surface of the bottom electrode.

Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

Abstract: A semiconductor device, such as an MRAM device, includes a stepped contact within a memory region that has a greater number of different contact structures (i.e., contact structures formed in different fabrication stages) relative to a logic region contact. The stepped contact includes a lower stepped contact and an upper stepped contact. The inclusion of the lower stepped contact allows for a relatively shorter upper stepped contact compared to the logic region contact. The stepped contact may allow the use of a multi-layer encapsulation spacer upon the sidewalls of a memory cell that fill out tight spacing therebetween, which may decrease the propensity of void formation and resulting shorting between neighboring memory cell features.

Abstract: A semiconductor structure that includes a metal level, a via located directly on top of a first portion of the metal level, wherein the via is tapered such that a smaller critical dimension is located at a top portion of the via and a larger critical dimension is located at a bottom portion of the via, and the bottom portion of the via is located adjacent the metal level, a dielectric cap located on top of a second portion of the metal level on which the via is not located directly thereon, and a next metal level that is located directly on the top portion of the via.

Abstract: A semiconductor structure comprises a memory device comprising a first electrode, at least one memory element layer disposed on the first electrode, and a second electrode disposed on the at least one memory element layer. An encapsulation layer is disposed around side surfaces of the memory device. The semiconductor structure also comprises a conductive cap layer disposed on a top surface of the encapsulation layer and around a portion of side surfaces of the encapsulation layer. A contact is disposed on the second electrode and extends around the side surfaces of the memory device.

Abstract: A BIOS setup environment configuration modification audit system includes a BIOS device that is included in a computing device and that is coupled to a component device in the computing device. The BIOS device enters a BIOS setup environment for the computing device and, while in the BIOS setup environment, detects component device configuration modification(s) to a configuration of the component device.

Abstract: A semiconductor structure comprises a bottom electrode contact, and a memory device comprising a bottom electrode disposed on the bottom electrode contact, at least one memory element layer disposed on the bottom electrode, and a top electrode disposed on the at least one memory element layer. A bit line contact is disposed on the top electrode and extends around sides of the memory device and of the bottom electrode contact. An encapsulation layer is disposed between the bit line contact and the sides of the memory device and of the bottom electrode contact.

Abstract: A semiconductor structure including a homogeneous interconnect structure embedded in a dielectric layer, where the homogeneous interconnect structure includes a third region vertically aligned above a second region vertically aligned above a first region, the third region includes three sections: an upper section including a first width; a middle section including an upper horizontal surface including the first width and a lower horizontal surface including a second width; and a lower section including the second width; where the first width is less than the second width; and the second region including a third width at an upper horizontal surface of the second region and a fourth width at a lower horizontal surface of the second region, where the third width is greater than the fourth width.

Abstract: A semiconductor structure comprises a reference layer of a magnetic random-access memory pillar structure, the reference layer having a first diameter, a free layer of the magnetic random-access memory pillar structure disposed over the reference layer, the free layer having a second diameter, and an electrode layer of the magnetic random-access memory pillar structure disposed over the free layer, the electrode layer having a third diameter. At least two of the first diameter, the second diameter and the third diameter are different.

Abstract: A package includes a redistribution structure, a bridge die, conductive pillars, connectors, a first die, first solder joints, and second solder joints. The bridge die includes a substrate, a dielectric layer disposed on the substrate, and routing patterns embedded in the dielectric layer. The conductive pillars are coupled to the redistribution structure at a position that is laterally offset from the bridge die. The connectors are coupled to the bridge die and the redistribution structure, such that the bridge die is electrically coupled to the redistribution structure through at least the connectors. The first solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the bridge die. The second solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the conductive pillars.

Abstract: A semiconductor structure is provided that includes a plurality of backside power islands, rather than backside power rails. The backside power islands are present in a first device track and a second device track. Each backside power island located in the first device track and the second device track are isolated by a first cut region, and the backside power islands that are located in the first device track are separated from the backside power islands located in the second device track by a second cut region. The second cut region is oriented perpendicular to the first cut region.

Abstract: A semiconductor structure including first metal lines embedded in a first dielectric layer, second metal lines embedded in a second dielectric layer, where the second metal lines arranged above the first metal lines, a top via extending between one of the first metal lines and one of the second metal lines, where the top via is self-aligned to the one of the first metal lines, and at least one air gap located adjacent to the top via between the first metal lines and the second metal lines.

Abstract: Fabrication method for forming a resistance tunable fuse stack structure includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer, a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting at least one of the first and second fuse conductive layers. Selection of various attributes of the fuse stack structure tunes a resistance of a fuse formed between the first and second fuse contacts.

Abstract: A first BEOL layer, including a first and a second signal line, a conformal dielectric surrounding an upper portion of a vertical sidewall of each of the first signal line and the second signal line, an air gap between the first and the second signal line, a vertical side boundary of the air gap is a vertical side surface of the first signal line. Forming a first and a second metal line in a sacrificial material in a first BEOL layer, removing the sacrificial material, forming a conformal dielectric surrounding vertical side surfaces of the first and the second metal line, an air gap between the first and the second metal line exposes an upper horizontal surface of a dielectric layer below the first BEOL layer, growing a dielectric selectively from an upper portion of the conformal dielectric, the air gap remains between the first and the second metal line.

Abstract: A semiconductor structure including a first stacked transistor structure adjacent to a second stacked transistor structure, and a first conductive structure in direct contact with and electrically connecting a bottom gate conductor of the first stacked transistor structure and a top gate conductor of the second stacked transistor structure.

Abstract: A structure including a homogeneous interconnect structure embedded in a dielectric layer, where the homogeneous interconnect structure includes a first region and a second region one above another, where the first region comprises a width which increases relative to height, and where the second region comprises a width which decreases relative to height.

Abstract: Embodiments of present invention provide a wiring structure. The wiring structure includes a metal line in a dielectric layer, where the metal line has a first sidewall and a second sidewall opposite the first sidewall and, from a bottom to a top thereof, includes at least a first section and a second section, where first and second sidewalls of the first section lean outwards from a bottom to a top of the first section, and first and second sidewalls of the second section lean inwards from a bottom to a top of the second section. A method of manufacturing the wiring structure is also provided.

Abstract: A dielectric layer is located on top of and in contact with a substrate. A conductive line located within the dialectic layer. A barrier layer on top of an in contact with the dielectric layer. The barrier layer is below the conductive line. A liner layer on top of and in contact with the barrier layer and below and in contact with the conductive line. A metal liner on top of and in contact with the conductive line. A capping layer on top of and in contact with the dielectric layer, the barrier layer, the liner layer, and the metal liner.

Abstract: A semiconductor structure that includes: a plurality of metal wires, and at least one dielectric substrate surrounding the plurality of metal wires. Each of the plurality of metal wires includes a tapered upper portion, a tapered lower portion, and a middle portion between the tapered upper portion and the tapered lower portion that is wider than the tapered upper and lower portions.