Abstract: A magnetic tunnel junction cell, a cross section with octagon profile, vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer, a bottom electrode with tapered side surface with a width at an upper surface greater than a width at a lower surface, the reference layer with vertical side surface perpendicular to an upper horizontal surface of the bottom electrode, the free layer and the tunneling barrier, each include a tapered side surface of the same angle, and each include a width at an upper surface less than a width at a lower surface. Forming a bottom electrode of a magnetic tunnel junction cell with a tapered side surface with a width at an upper surface greater than a width at a lower surface, forming a reference layer with vertical side surface perpendicular to an upper surface of the bottom electrode.

Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a sacrificial dielectric layer on top of a bottom contact; forming a stack of a first ferromagnetic layer, a tunnel barrier layer, a second ferromagnetic layer, and at least one hard mask on top of the sacrificial dielectric layer; forming an interlevel-dielectric (ILD) layer surrounding the stack; creating one or more via holes in the ILD layer to expose the sacrificial dielectric layer; selectively removing the sacrificial dielectric layer to create an opening underneath the first ferromagnetic layer; filling the opening with a first conductive material to form a bottom electrode; removing the at least one hard mask to expose the second ferromagnetic layer; and forming a top electrode of a second conductive material on top of the second ferromagnetic layer. An MRAM structure formed thereby is also provided.

Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a blanket first ferromagnetic layer on top of a bottom electrode; etching the blanket first ferromagnetic layer to form a first ferromagnetic layer, the first ferromagnetic layer having an upper portion that has an angled edge and a lower portion that has a vertical edge; forming a blanket tunnel barrier layer on top of the first ferromagnetic layer and a blanket second ferromagnetic layer on top of the blanket tunnel barrier layer; patterning the blanket tunnel barrier layer and the blanket second ferromagnetic layer to form a tunnel barrier layer and a second ferromagnetic layer; and forming a top electrode on top of the second ferromagnetic layer. A MRAM structure formed thereby is also provided.

Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming at least one magnetic tunnel junction (MTJ) stack on top of a supporting structure; forming a conformal liner surrounding a sidewall of the MTJ stack; forming a first dielectric layer surrounding the conformal liner; selectively forming a metal oxide layer on top of the conformal liner and the first dielectric layer, the metal oxide layer having at least a first opening that exposes a top surface of the MTJ stack; and forming a top contact contacting the top surface of the MTJ stack through the first opening in the metal oxide layer. An MRAM structure formed thereby is also provided.

Abstract: A semiconductor structure includes a shallow trench isolation region disposed within a semiconductor substrate, and a conductive spacer disposed within the shallow trench isolation region.

Abstract: A semiconductor device includes a bottom electrode contact disposed over one or more of a plurality of conductive lines, magnetoresistive random access memory (MRAM) pillars constructed over the bottom electrode contact, an encapsulation layer section disposed between a pair of the MRAM pillars such that an aspect ratio of a tight pitch gap between the pair of the MRAM pillars is reduced, and a dielectric disposed within the encapsulation layer section, wherein the dielectric fills an entirety of a space defined within the encapsulation layer section. The MRAM pillars have a generally rectangular-shaped or cone-shaped configuration and the encapsulation layer section has a generally U-shaped or V-shaped configuration.

Abstract: A wire interconnect, a wire interconnect structure, and a method to form wire interconnect structures with locally widened profiles. The wire interconnect may include a first portion of the wire interconnect with a first width. The wire interconnect may also include a second portion of the wire interconnect with a second width, where the second width is greater than the first width, and where the second portion of the wire interconnect is above the first portion of the wire interconnect. The wire interconnect may also include a third portion of the wire interconnect with a third width, where the third width is less than the second width, and where the third portion of the wire interconnect is above the second portion of the wire interconnect.

Abstract: A first power rail directly below and connected to a source-drain epitaxy region of a positive field effect transistor (p-FET) region, a second power rail directly below and connected to a source-drain epitaxy region of a negative field effect transistor (n-FET) region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other. Forming a first power rail by subtractive metal etch, where the first power rail is directly below and connected to a source-drain epitaxy region of a p-FET region and forming a second power rail by damascene process, where the second power rail is directly below and connected to a source-drain epitaxy region of an n-FET region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other.

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack vertically aligned between an annular shaped bottom electrode and an annular shaped top electrode. A semiconductor device including a MTJ stack, vertically aligned between an annular shaped bottom electrode and an annular shaped top electrode, and an encapsulation layer surrounding vertical side surfaces of the MTJ stack, wherein the encapsulation layer does not surround the top electrode nor the bottom electrode. Forming a bottom electrode in a first inter-layer dielectric, forming a reference layer on the first inter-layer dielectric and on the bottom electrode, forming a tunnel barrier layer on the reference layer, forming a free layer on the tunnel barrier layer and patterning the reference layer, the tunnel barrier layer and the free layer into a magnetic tunnel function (MTJ) stack vertically aligned over the bottom electrode, while not patterning the bottom electrode nor the first inter-layer dielectric.

Abstract: An interconnect structure includes a diffusion barrier layer disposed on exterior surfaces of an opening in a dielectric layer. A top surface of the diffusion barrier layer is below a top surface of the opening. A liner layer is disposed on a bottom surface and sidewalls of the diffusion barrier layer. A spacer layer is disposed on the top surface of the diffusion barrier layer and the liner layer and exposed sidewalls of the opening. An interconnect metal is disposed on the liner layer and the spacer layer. A metal cap is disposed on the interconnect metal.

Abstract: A semiconductor structure is presented including a device layer having a plurality of active devices, back-end-of-line (BEOL) components disposed under the device layer, a power distribution network (PDN) disposed over the device layer, and backside transistors disposed on a single crystal silicon (Si) layer disposed over the PDN. A through silicon via (TSV) extends from the backside transistors disposed on the single crystal Si layer through the BEOL. An upper TSV (uTSV) extends from the PDN through the backside transistors disposed on the single crystal Si layer to additional interconnects.

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines in direct contact with a top surface of one or more devices and one or more vias in direct contact with top surfaces of the one or more metal lines. The interconnect structure also includes one or more dielectric pillars in direct contact with the top surface of the one or more devices. A height of a top surface of the one or more dielectric pillars above the one or more devices is equal to a height of a top surface of the one or more vias above the one or more devices.

Abstract: A CMOS apparatus includes an n-doped field effect transistor (nFET); and a p-doped field effect transistor (pFET), each of which has a source structure and a drain structure. A common backside drain contact, which is disposed at the backside surface of the nFET and the pFET, electrically connects the nFET drain structure and the pFET drain structure to a backside interconnect layer.

Abstract: A semiconductor structure is presented including a first memory array and a second memory array directly connected to the first memory array by nanosheet stacks and backside contacts. The first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (CMOS) wafer. The nanosheet stacks separate the first memory array from the second memory array so that two different types of memory devices are integrated together into a single CMOS chip.

Abstract: A semiconductor structure includes a power distribution structure disposed on a first wafer, an interconnect structure disposed on the first wafer and a second wafer, and at least one decoupling capacitor connected between the power distribution structure and the interconnect structure.

Abstract: A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.

Abstract: A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a semiconductor structure. The semiconductor structure may include an embedded magnetic random access memory (MRAM) array electrically connected between a bottom metal level and a top metal level. The MRAM array may include a first tier with first MRAM cells and first vias above the first MRAM cells, and a second tier with second MRAM cells and second vias below the second MRAM cells.

Abstract: A method to form a semiconductor structure for a magnetoresistive random-access memory (MRAM) device where the material for the top electrode and the bottom electrode is deposited in a single process. The method includes conformally depositing an electrode material over a magnetic tunnel junction (MTJ) pillar, under the MTJ pillar, around a spacer encapsulating and extending above the MTJ pillar. The method includes recessing the electrode material to form a thinner portion of the electrode material over the MTJ pillar. The thinner portion of the electrode material forms a thinner portion of the electrode material over the MTJ pillar that is a top electrode. The portion of the electrode material under the MTJ pillar forms a bottom electrode that is thicker than the top electrode.

Abstract: A microelectronic structure including a first nano device, where the first nano device includes a plurality of transistors. A bottom dielectric isolation located on the backside of each of the plurality of transistors of the first nano device. A separating dielectric layer located on the backside of the bottom dielectric isolation layer, where the separating dielectric layer is a continuous layer on the backside of each of the plurality of transistors of the first nano device.