Patents by Inventor Chih-Chao Yang

Chih-Chao Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190157202
    Abstract: A structure comprising a first dielectric layer embedded with a first interconnect structure. An insulator layer is disposed on the first dielectric layer. A second dielectric layer is disposed on the insulator layer. A via resides within the second dielectric layer. A second interconnect structure is isolated from the first dielectric layer. A first portion of a bottom surface of the via resides on a top surface of the insulator layer. A second portion of the bottom surface of the via resides on a first portion of a top surface of the first interconnect structure.
    Type: Application
    Filed: January 2, 2019
    Publication date: May 23, 2019
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Publication number: 20190157088
    Abstract: After forming a contact opening in a dielectric material layer located over a substrate, a metal liner layer comprising a nitride of an alloy and a metal contact layer comprising the alloy that provides the metal liner layer are deposited in-situ in the contact opening by sputter deposition in a single process and without an air break. Compositions of the metal liner layer and the metal contact layer can be changed by varying gas compositions employed in the sputtering process.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 23, 2019
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10297750
    Abstract: A method is presented for forming a semiconductor device. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form a plurality of trenches for receiving a first conducting material, forming a resistive switching memory element over at least one trench of the plurality of trenches, the resistive switching memory element having a conducting cap formed thereon, and depositing a dielectric cap over the trenches. The method further includes etching portions of the insulating layer to expose a section of the dielectric cap formed over the resistive switching memory element, etching the exposed section of the dielectric cap to expose the conducting cap of the resistive switching memory element, and forming a barrier layer in direct contact with the exposed section of the conducting cap.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10297569
    Abstract: A first semiconductor structure including a first bonding oxide layer having a first metallic bonding structure embedded therein and a second semiconductor structure including a second bonding oxide layer having a second metallic bonding structure embedded therein are provided. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. Each nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layer and nitridized metallic regions located in an upper portion of the metallic bonding structures. The nitrogen within the nitridized metallic regions is then removed to restore the upper portion of the metallic bonding structures to its original composition. Bonding is performed to form a dielectric bonding interface between the nitridized oxide regions present in the first and second structures, and a metallic bonding interface between the first and second metallic bonding structures.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Publication number: 20190148296
    Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 16, 2019
    Inventors: Benjamin D. Briggs, Elbert E. Huang, RAGHUVEER R. PATLOLLA, CORNELIUS BROWN PEETHALA, DAVID L. RATH, CHIH-CHAO YANG
  • Publication number: 20190148637
    Abstract: A method is presented for forming a semiconductor device. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form a plurality of trenches for receiving a first conducting material, forming a resistive switching memory element over at least one trench of the plurality of trenches, the resistive switching memory element having a conducting cap formed thereon, and depositing a dielectric cap over the trenches. The method further includes etching portions of the insulating layer to expose a section of the dielectric cap formed over the resistive switching memory element, etching the exposed section of the dielectric cap to expose the conducting cap of the resistive switching memory element, and forming a barrier layer in direct contact with the exposed section of the conducting cap.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 16, 2019
    Inventors: Takashi Ando, Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10290541
    Abstract: A semiconductor structure includes a dielectric layer having a trench formed therein and a barrier layer formed on a bottom and sidewalls of the trench, and on a top surface of the dielectric layer. The trench comprises a flared top gap opening and additional area at the bottom such that the top and bottom of the trench are wider than sidewalls of the trench. A thickness of the barrier layer on the bottom of the trench and on the top surface of the dielectric layer is controlled using one or more cycles comprising forming an oxidized layer using a neutral beam oxidation and removing the oxidized layer using an etching process, such that the thickness of the barrier layer on the bottom of the trench and on the top surface of the dielectric layer is substantially the same as the thickness of the barrier layer on sidewalls of the trench.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Cornelius Brown Peethala, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20190139821
    Abstract: Advanced dual damascene interconnects that exhibit controlled via resistance and, in some instances, controlled line resistance are provided. In one embodiment, the structure includes an interconnect level having a combined via/line opening located therein. A diffusion barrier liner is located in at least the via portion of the combined via/line opening. A first metallic structure composed of an electrically conductive metal or metal alloy having a first bulk resistivity is located in at least the via portion of the combined via/line opening. A second metallic structure composed of an electrically conductive metal or metal alloy that has a second bulk resistivity that is higher than the first bulk resistivity is located in at least the line portion of the combined via/line opening. In accordance with the present application, second metallic structure is in direct contact with the first metallic structure.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 9, 2019
    Inventors: Chih-Chao Yang, Theo Standaert
  • Publication number: 20190139904
    Abstract: An interconnect level is provided on a surface of a substrate that has improved crack stop capability. The interconnect level includes at least one wiring region including an electrically conductive structure embedded in an interconnect dielectric material having a dielectric constant of less than 4.0, and a crack stop region laterally surrounding the wiring region. The crack stop region includes a crack stop dielectric material having a dielectric constant greater than the dielectric constant of the interconnect dielectric material. The crack stop region may be devoid of any metallic structure, or it may contain a metallic structure. The metallic structure in the crack stop region, which is embedded in the crack stop dielectric material, may be composed of a same, or different, electrically conductive metal or metal alloy as the electrically conductive structure embedded in the interconnect dielectric material.
    Type: Application
    Filed: November 7, 2017
    Publication date: May 9, 2019
    Inventors: Baozhen Li, Chih-Chao Yang, Griselda Bonilla
  • Publication number: 20190139820
    Abstract: Advanced dual damascene interconnects have been provided in which a metallic seed liner composed of an electrically conductive metal or metal alloy having a first bulk resistivity is located on sidewall surfaces and a bottom wall of a first metallic structure that is present in a via portion of a combined via/line opening that is present in an interconnect dielectric material layer. The first metallic structure is composed of an electrically conductive metal or metal alloy that has a second bulk resistivity that is higher than the first bulk resistivity. In some embodiments, a second metal structure is present on a topmost surface of the first metallic structure. The second metallic structure is composed of an electrically conductive metal or metal alloy that differs from the electrically conductive metal or metal alloy of the first metallic structure.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 9, 2019
    Inventors: Chih-Chao Yang, Theo Standaert
  • Patent number: 10283583
    Abstract: The present application provides a 3D resistor structure that is embedded within an interconnect dielectric material in which the resistivity of an electrical conducting resistive material of the 3D resistor structure can be tuned to a desired resistivity during the manufacturing of the 3D resistor structure. Notably, a patterned doped metallic insulator is formed straddling over an dielectric pillar. A controlled surface treatment process is then performed to an upper portion of the patterned doped metallic insulator to convert the upper portion of the patterned doped metallic insulator into an electrical conducting resistive material. An interconnect dielectric material can then be formed to embed the entirety of the remaining patterned doped metallic insulator and the electrical conducting resistive material.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 10276435
    Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 10276649
    Abstract: A semiconductor structure containing at least two metal resistor structures having different resistivities is provided and includes a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first nitridized dielectric surface layer portion having a first nitrogen content, a first metal layer portion and a first nitridized metal surface layer. A second metal resistor structure is located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second nitridized dielectric surface layer portion having a second nitrogen content, a second metal layer portion and a second nitridized metal surface layer. The second nitrogen content of the second nitridized dielectric surface layer portion differs from the first nitrogen content of the first nitridized dielectric surface layer portion.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 10276501
    Abstract: An integrated circuit device includes a substrate including a dielectric layer patterned with a set of conductive line trenches, each conductive line trench having parallel vertical sidewalls and a horizontal bottom. A liner which is an alloy of a first metal and a selected element formed at interfaces of the metal layer and a surface of the dielectric and is created by an anneal and reflow process. The first metal having a first conductivity in a pure form. A second metal layer fills the set of conductive line trenches, the second metal having a second conductivity higher than the first conductivity.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel C Edelstein, Chih-Chao Yang
  • Patent number: 10276503
    Abstract: A method includes forming a dielectric layer and forming a metallic conductor at least partially in the dielectric layer. Formation of the metallic conductor at least partially in the dielectric layer includes performing a planarization process. The method further includes treating respective surface areas of the dielectric layer and the metallic conductor, after the planarization process, to modify the respective surface areas of the dielectric layer and the metallic conductor. In one example, the surface treatment is a neutral atom beam treatment.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Publication number: 20190115419
    Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.
    Type: Application
    Filed: November 17, 2017
    Publication date: April 18, 2019
    Inventors: Baozhen Li, Kirk Peterson, John Sheets, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang
  • Publication number: 20190115418
    Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 18, 2019
    Inventors: Baozhen Li, Kirk Peterson, John Sheets, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang
  • Publication number: 20190115421
    Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.
    Type: Application
    Filed: November 17, 2017
    Publication date: April 18, 2019
    Inventors: Baozhen Li, Kirk Peterson, John Sheets, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang
  • Publication number: 20190115420
    Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.
    Type: Application
    Filed: November 17, 2017
    Publication date: April 18, 2019
    Inventors: Baozhen Li, Kirk Peterson, John Sheets, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang
  • Patent number: 10256185
    Abstract: A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Roger A. Quon, Hosadurga K. Shobha, Terry A. Spooner, Wei Wang, Chih-Chao Yang