Abstract: Embodiments of the present invention are directed to methods and resulting structures for integrated circuits having metal-insulator-metal (MIM) capacitors that serve as both decoupling capacitors and crack stops. In a non-limiting embodiment, an interconnect is formed on a first portion of a substrate in an interior region of the integrated circuit. A second portion of the substrate is exposed in an edge region of the integrated circuit. A MIM capacitor is formed over the second portion of the substrate in the edge region. The MIM capacitor includes two or more plates and one or more dielectric layers. Each dielectric layer is positioned between an adjacent pair of the two or more plates and a portion of the two or more plates extends over the interconnect in the interior region. A plate of the two or more plates is electrically coupled to a last metal wiring level of the interconnect.

Abstract: A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.

Abstract: A metallic hardmask is formed having a selected stress designed to create a selected amount of positive wafer bow. In preferred embodiments, metallic hardmask is disposed on a memory pillar layer over a wafer substrate. A set of memory pillars using the metal hardmask. Because of the positive wafer bow, the patterned set of memory pillars at both the edges and the central portion of the wafer substrate are aligned with a respective contact for a memory device. A positive wafer bow is defined as a bowed wafer substrate where a central portion of a patterned side of the wafer substrate is lower than edges of the wafer substrate.

Abstract: A structure and a method for fabricating interconnections for an integrated circuit device are described. The method forms a metal interconnection pattern having a first barrier layer and a copper layer in a set of trenches in a first dielectric layer over a substrate. In a selected area, the first dielectric layer is removed to so that the first barrier layer can be removed at the exposed vertical surfaces. A thin second barrier layer is deposited over the exposed vertical surfaces of the first copper layer. A structure includes a first feature formed in a first dielectric layer which has a first barrier layer disposed on vertical surfaces of the first dielectric layer and surrounds opposing vertical surfaces and a bottom surface of a copper layer.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a back end of line (BEOL) wiring layer including metal lines and a first area between the metal lines. The integrated circuit structure also includes a metal-insulator-metal (MIM) capacitor formed in the first area. The MIM capacitor includes a first electrode, a first dielectric layer formed on the first electrode, a second electrode formed on the first dielectric layer, a second dielectric layer formed on the second electrode, a third electrode formed on the second dielectric layer, a third dielectric layer formed on the third electrode, a fourth electrode formed on the third dielectric layer, a first metal interconnect electrically connecting the first electrode and the third electrode, and a second metal interconnect electrically connecting the second electrode to the fourth electrode.

Abstract: A magnetic tunnel junction pillar is positioned above a bottom electrode composed of a metal-oxide region in contact with a first portion of the magnetic tunnel junction pillar and a metal region surrounding the metal-oxide region. A sidewall spacer is positioned along sidewalls of the magnetic tunnel junction pillar, and the metal region is in contact with a bottom surface of the sidewall spacer and a second portion of the magnetic tunnel junction pillar.

Abstract: Method and a magnetoresistive random access memory (MRAM) structure is provided. The structure includes an interconnect and a multilayered magnetic tunnel junction (MTJ) pillar located on the interconnect and having an outermost sidewall. The MTJ pillar includes an electrode layer electrically connecting the MTJ pillar to the interconnect. The electrode layer includes an insulative material at an outermost portion of the electrode layer and a conductive material at a first inner portion of the electrode layer disposed radially inward from the outermost portion of the electrode layer.

Abstract: Embodiments of the present invention are directed to subtractive processing methods and resulting structures for semiconductor devices having decoupled interconnects. In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A conductive pillar is formed over the first conductive line and a liner is formed in a trench adjacent to the first conductive line. A portion of the liner extends over the conductive pillar. A lower metal line and a top via are subtractively formed on the liner in the trench.

Abstract: A first metal interconnection pattern is formed over a substrate. A spacer layer is selectively deposited on the exposed surfaces of the first metal interconnection pattern. Subsequently, a metal overburden layer is deposited on the spacer layer. The excess portion of the metal overburden layer is removed, i.e., that portion deposited over a top surface of the metal interconnection pattern and the spacer layer. This forms a second metal interconnection pattern. The elements of the second metal interconnection pattern are located between respective elements of the first metal interconnection pattern.

Abstract: Method and resistive structure is provided herein. The resistive structure includes a semiconductor substrate comprising one or more circuit elements and a first interconnect layer disposed on the substrate. The first interconnect layer is between a resistive layer and the semiconductor substrate. A dielectric layer is disposed between the first interconnect layer and the resistive layer. A via extending through the dielectric layer forms an electrical connection between the first interconnect layer and the resistive layer.

Abstract: An MRAM device is provided. The MRAM device includes a semiconductor device comprising a bottom contact electrode (BEC), and an MRAM stack formed on the BEC. A width of an upper portion of the BEC is less than a width of the MRAM stack.

Abstract: A magneto-resistive random access memory with segmented bottom electrode includes a magnetic tunnel junction pillar above a first portion of a bottom electrode layer, the first portion of the bottom electrode layer includes a metal region. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar and above a second portion of the bottom electrode layer including a metal-oxide region. The first portion of the bottom electrode layer composed of the metal region and the second portion of the bottom electrode layer composed of the metal-oxide region form the segmented bottom electrode.

Abstract: Embodiments of the invention include a method of forming portions of a multi-layer integrated circuit (IC) structure. The method includes forming a back-end-of-line (BEOL) layer having a BEOL layer topography. An etch-stop layer is formed over the BEOL layer topography. A metal is formed over the etch-stop layer. A first planarization operation is applied to remove a first portion of the metal. The etch-stop layer is used to stop the first planarization operation. A second planarization operation is applied to remove the etch-stop layer and a second portion of the metal.

Abstract: Embodiments of the invention are directed to an integrated circuit (IC) structure that includes a memory element a non-sacrificial hardmask stack over the memory element. The non-sacrificial hardmask stack includes a first hardmask region and a second hardmask region. A compressive stress level of the first hardmask region is greater than a compressive stress level of the second hardmask region.

Abstract: A semiconductor device and formation thereof. The semiconductor device includes a memory device located on top of a first bottom interconnect, wherein the first bottom interconnect is embedded in a first dielectric layer. The semiconductor device further includes a second bottom interconnect embedded in the first dielectric layer, wherein the second bottom interconnect is adjacent to the first bottom interconnect. A top surface of the second bottom interconnect is recessed relative to a top surface of the first bottom interconnect.

Abstract: Embodiments of the present invention are directed to in-situ wafer feedback schemes and systems for providing localized process-based compensation on a semiconductor wafer. In a non-limiting embodiment of the invention, a plurality of test structures are formed on a surface of a semiconductor wafer. The semiconductor wafer is placed under a detection surface of an in-situ feedback tool comprising one or more sensors. The in-situ feedback tool measures a property of each of the plurality of test structures and determines a local condition of the semiconductor wafer for each measured property of the plurality of test structures. A localized process-based compensation is provided on the surface of the semiconductor wafer for each local condition.

Abstract: An MRAM device is provided. The MRAM device includes a first dielectric cap layer formed on an underlying layer, a second dielectric cap layer formed on the first dielectric cap layer, the first dielectric cap layer including a lower-? material than that of the second dielectric cap layer. The MRAM device also includes a bottom electrode contact (BEC) formed through the first dielectric cap layer and the second dielectric cap layer, an MRAM stack formed on the BEC, and wherein the second dielectric cap layer surrounds an upper portion of the BEC.

Abstract: A semiconductor device and formation thereof. The semiconductor device including: a first bottom interconnect formed within a first dielectric layer and located within a logic area of the semiconductor device; a second bottom interconnect formed within the first dielectric layer and located within a memory area of the semiconductor device; and a memory device formed on top of the second bottom interconnect located within the memory area of the semiconductor device, wherein: a first metal material used to form the first bottom interconnect located in the logic area is different than a second metal material used to form the second bottom interconnect located in the memory area.

Abstract: A semiconductor structure includes a resistance tunable fuse stack structure. A fabrication method for forming the same includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer. The method forms a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer, the layers are interleaved in a stack forming a fuse stack structure. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting the first and second fuse conductive layers.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for integrated circuits having metal-insulator-metal (MIM) capacitors that serve as both decoupling capacitors and crack stops. In a non-limiting embodiment, an interconnect is formed on a first portion of a substrate in an interior region of the integrated circuit. A second portion of the substrate is exposed in an edge region of the integrated circuit. A MIM capacitor is formed over the second portion of the substrate in the edge region. The MIM capacitor includes two or more plates and one or more dielectric layers. Each dielectric layer is positioned between an adjacent pair of the two or more plates and a portion of the two or more plates extends over the interconnect in the interior region. A plate of the two or more plates is electrically coupled to a last metal wiring level of the interconnect.