Patents by Inventor Chih-Chao Yang

Chih-Chao Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SUBTRACTIVE LINE WITH DAMASCENE TOP VIA
    Publication number: 20230178421
    Abstract: Embodiments disclosed herein describe semiconductor devices that include semiconductor structures and methods of forming the semiconductor structures. The methods may include forming a subtractive line from a bottom metal layer and a sacrificial hard mask above the bottom metal layer, depositing a scaffolding material around the subtractive line, forming a via mask over a via portion of the sacrificial hard mask and the scaffolding material, etching the sacrificial hard mask that is not covered by the via mask, to form a sacrificial via, removing the via mask and the scaffolding material, depositing a low-? layer around the subtractive line and the sacrificial via, removing the sacrificial via to form a via hole within the low-? layer, and forming a top via by metallizing the via hole.
    Type: Application
    Filed: December 7, 2021
    Publication date: June 8, 2023
    Inventors: Chanro Park, Koichi Motoyama, Hsueh-Chung Chen, Chih-Chao Yang
  • TOP ELECTRODE TO METAL LINE CONNECTION FOR MAGNETO-RESISTIVE RANDOM-ACCESS MEMORY STACK HEIGHT REDUCTION
    Publication number: 20230180621
    Abstract: A magneto-resistive random access memory device includes a top electrode electrically connected to a conductive interconnect through a metal capping layer located above a top surface and opposite sidewalls of the top electrode, the conductive interconnect is located on opposite sidewalls of the metal capping layer with a top surface of the metal capping layer being coplanar with a top surface of the conductive interconnect.
    Type: Application
    Filed: December 3, 2021
    Publication date: June 8, 2023
    Inventors: Ruilong Xie, Tao Li, Tsung-Sheng Kang, Alexander Reznicek, Chih-Chao Yang
  • SUBTRACTIVE TOP VIA AS A BOTTOM ELECTRODE CONTACT FOR AN EMBEDDED MEMORY
    Publication number: 20230180618
    Abstract: Embodiments of the invention include a subtractive top via as a bottom electrode contact for an embedded memory structure. Forming the bottom electrode contact includes depositing a conductive material on an underlayer and etching the conductive material to form an extended via and a conductive pad as an integral unit. The extended via extends from the conductive pad such that the extended via is adjacent to a memory structure, the extended via being formed as a first contact for the memory structure.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Inventors: Ashim Dutta, Chih-Chao Yang
  • MAGNETIC TUNNEL JUNCTION WITH AN ETCHED BOTTOM ELECTRODE HAVING NON-PLANAR SIDEWALLS
    Publication number: 20230180622
    Abstract: Embodiments of the invention are directed to a structure comprising a magnetic tunnel junction (MTJ) element and an etched bottom electrode (BE) communicatively coupled to the MTJ element. The etched BE includes a substantially non-planar BE sidewall.
    Type: Application
    Filed: December 7, 2021
    Publication date: June 8, 2023
    Inventors: Koichi Motoyama, Oscar van der Straten, Joseph F. Maniscalco, Chih-Chao Yang
  • METAL-INSULATOR-METAL CAPACITOR STRUCTURE WITH ENLARGED CAPACITOR AREA
    Publication number: 20230178588
    Abstract: A MIM capacitor and related methods of fabricating the MIM capacitor. The MIM capacitor includes a bottom capacitor plate including a plurality of trenches defined therein, and a top capacitor plate. The MIM capacitor also includes a capacitor insulating layer disposed between the top capacitor plate and the bottom capacitor plate and within the plurality of trenches. Further, the MIM capacitor includes a first electrode electrically connected to the bottom capacitor plate, and a second electrode electrically connected to the top capacitor plate.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Inventors: CHANRO PARK, Koichi Motoyama, Kenneth Chun Kuen Cheng, Chih-Chao Yang
  • ACCURATE METAL LINE AND VIA HEIGHT CONTROL FOR TOP VIA PROCESS
    Publication number: 20230178429
    Abstract: A method of manufacturing an interconnect structure for a semiconductor device is provided. The method includes forming a metal interconnect layer on a substrate. The method includes forming a hardmask on the metal interconnect layer, patterning the metal interconnect layer and hardmask, forming a sacrificial material layer to overfill the patterned metal interconnect layer and hardmask, and selectively removing a portion of the sacrificial layer and the hardmask to form a via opening. The method also includes forming a via on the metal interconnect layer in the via opening by a selective metal growth process.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 8, 2023
    Inventors: TSUNG-SHENG KANG, RUILONG XIE, TAO LI, CHIH-CHAO YANG
  • ADVANCED METAL INTERCONNECT
    Publication number: 20230178431
    Abstract: A first metal layer is deposited on a substrate. The first metal layer is etched to form one or more metal lines and expose portions of the substrate. A second metal layer is deposited on the exposed portions of the substrate between the one or more metal lines. The first metal layer is patterned to form one or more vertical vias. A dielectric layer is deposited on the exposed portions of the substrate between an exposed sidewalls of the first metal layer and an exposed sidewalls of the second metal layer.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 8, 2023
    Inventors: Ashim Dutta, Chih-Chao Yang, Lawrence A. Clevenger, Ruilong Xie
  • DIELECTRIC FILL FOR TIGHT PITCH MRAM PILLAR ARRAY
    Publication number: 20230178129
    Abstract: A semiconductor device includes a bottom electrode contact disposed over one or more of a plurality of conductive lines, magnetoresistive random access memory (MRAM) pillars constructed over the bottom electrode contact, an encapsulation layer section disposed between a pair of the MRAM pillars such that an aspect ratio of a tight pitch gap between the pair of the MRAM pillars is reduced, and a dielectric disposed within the encapsulation layer section, wherein the dielectric fills an entirety of a space defined within the encapsulation layer section. The MRAM pillars have a generally rectangular-shaped or cone-shaped configuration and the encapsulation layer section has a generally U-shaped or V-shaped configuration.
    Type: Application
    Filed: December 3, 2021
    Publication date: June 8, 2023
    Inventors: Ashim Dutta, Chih-Chao Yang, Theodorus E. Standaert, Daniel Charles Edelstein
  • TOP VIA WITH PROTECTIVE LINER
    Publication number: 20230178423
    Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines and one or more top vias in direct contact with a top surface of the one or more metal lines. The interconnect structure also includes a liner formed on sidewalls of the one or more top vias and top portions of the one or more metal lines.
    Type: Application
    Filed: December 3, 2021
    Publication date: June 8, 2023
    Inventors: Tao Li, Ruilong Xie, Tsung-Sheng Kang, Chih-Chao Yang
  • VIA PATTERNING FOR INTEGRATED CIRCUITS
    Publication number: 20230170298
    Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines in direct contact with a top surface of one or more devices and one or more vias in direct contact with top surfaces of the one or more metal lines. The interconnect structure also includes one or more dielectric pillars in direct contact with the top surface of the one or more devices. A height of a top surface of the one or more dielectric pillars above the one or more devices is equal to a height of a top surface of the one or more vias above the one or more devices.
    Type: Application
    Filed: December 1, 2021
    Publication date: June 1, 2023
    Inventors: Tao Li, Ruilong Xie, Tsung-Sheng Kang, Chih-Chao Yang
  • PROBE PAD WITH BUILT-IN INTERCONNECT STRUCTURE
    Publication number: 20230170266
    Abstract: A system includes a wafer including at least an electronic component and a probe pad including a built-in back-end-of-line (BEOL) interconnect structure to test the electronic component. The electronic component is tested by the probe pad without building full BEOL interconnect circuits on the wafer. The probe pad is aligned with the wafer by using alignment marks. A prober alignment camera is employed to locate the alignment marks.
    Type: Application
    Filed: November 29, 2021
    Publication date: June 1, 2023
    Inventors: Ashim Dutta, Ruturaj Nandkumar Pujari, Saumya Sharma, Chih-Chao Yang
  • DUAL-DAMASCENE FAV INTERCONNECTS WITH DIELECTRIC PLUG
    Publication number: 20230170253
    Abstract: The structure comprises a first low-k dielectric layer on top of a substrate. The structure comprises one or more trenches within the first low-k dielectric layer. The structure comprises a first barrier layer on the first low-k dielectric layer, a first liner layer on top of the first barrier layer and a first metal layer on top of the first liner layer, wherein a top of the first barrier layer, the first liner layer, and the first metal layer are at least 5 nm below a top of the first low-k dielectric layer. The structure comprises a dielectric cap between portions the first low-k dielectric layer and a second low-k dielectric layer. The structure comprises a dielectric plug between portions of the first low-k dielectric layer and the second low-dielectric layer.
    Type: Application
    Filed: December 1, 2021
    Publication date: June 1, 2023
    Inventors: CHANRO PARK, Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang
  • TALL BOTTOM ELECTRODE STRUCTURE IN EMBEDDED MAGNETORESISTIVE RANDOM-ACCESS MEMORY
    Publication number: 20230172073
    Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure is provided, the memory area interconnect structure comprising metal interconnects formed in the substrate. A metal line on a metal interconnect of the non-memory area interconnect structure is formed. A first dielectric layer on exposed surfaces of the non-memory area is formed. A hardmask is formed on the dielectric layer. A second dielectric layer is formed on exposed surfaces of the memory area. A bottom metal contact is formed in a trench, a bottom surface of the bottom metal contact on a top surface of a first metal interconnect of the memory area interconnect structure. A memory element stack pillar is formed on the bottom metal contact.
    Type: Application
    Filed: December 1, 2021
    Publication date: June 1, 2023
    Inventors: Ashim Dutta, Lili Cheng, Chih-Chao Yang
  • EMBEDDED MAGNETORESISTIVE RANDOM ACCESS MEMORY TOP ELECTRODE STRUCTURE
    Publication number: 20230157181
    Abstract: An approach to provide a pillar-type memory device with a bump of a conductive material on a top electrode of the pillar-type memory device. The top electrode is composed of a thin layer of the top electrode material. The bump of the conductive material increases the height of the top electrode after pillar formation for the pillar-type memory device. The pillar-type memory device includes the bump of the conductive material with a semi-sphere-like bump of the conductive metal that is slightly wider than the top electrode of the pillar-type memory device. A contact connects with the bump of the conductive material on the top electrode.
    Type: Application
    Filed: November 17, 2021
    Publication date: May 18, 2023
    Inventors: Ashim Dutta, Chih-Chao Yang
  • ETCHING OF MAGNETIC TUNNEL JUNCTION (MTJ) STACK FOR MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM)
    Publication number: 20230144157
    Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first set of spacers are formed on the sidewalls of a bottom electrode. A reference layer is formed on the spacers and the bottom electrode. A second set of spacers are formed on the sidewalls of the first set of spacers and the reference layer. A tunnel barrier is formed on the reference layer and the second set of spacers. A free layer is formed on the tunnel barrier, where a width of the free layer is greater than a width of the reference layer. A metal hardmask is formed on the free layer. A third set of spacers are formed on the sidewalls of the metal hardmask, the free layer, the tunnel barrier, and the second set of spacers.
    Type: Application
    Filed: November 7, 2021
    Publication date: May 11, 2023
    Inventors: Koichi Motoyama, Oscar van der Straten, Joseph F. Maniscalco, Chih-Chao Yang
  • ELECTRONIC FUSE STRUCTURE EMBEDDED IN TOP VIA
    Publication number: 20230144660
    Abstract: Provided is a semiconductor device and corresponding method of fabricating the same. The semiconductor device comprises a plurality of bottom lines. One or more top vias are arranged on top of the plurality of bottom lines. One or more electronic fuses (eFuses) are also arranged on top of the plurality of bottom lines. Each eFuse of the one or more eFuses is a via having a smaller critical dimension that the one or more top vias. A plurality of top lines are arranged on top of the one or more top vias and the one or more eFuses.
    Type: Application
    Filed: November 5, 2021
    Publication date: May 11, 2023
    Inventors: Koichi Motoyama, CHANRO PARK, Hsueh-Chung Chen, Chih-Chao Yang
  • Fabrication of phase change memory cell in integrated circuit
    Patent number: 11647681
    Abstract: A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: May 9, 2023
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Chih-Chao Yang, Andrew Tae Kim, Barry Linder
  • TOP VIA CONTAINING RANDOM-ACCESS MEMORY CROSS-BAR ARRAY
    Publication number: 20230139648
    Abstract: Disclosed is a memory device. The memory device comprises a cross-bar array of memory cells. The cross-bar array of memory cells comprises a plurality of bottom level lines arranged in a first direction. The cross-bar array of memory cells further comprises a plurality of vias arranged on top of each of the plurality of bottom level lines. The cross-bar array of memory cells further comprises a plurality of memory cells. Each memory cell is arranged on top of one of the plurality of vias. The cross-bar array of memory cells further comprises a plurality of top level lines arranged in a second direction that is substantially perpendicular to the first direction. Each top level line is arranged on top of and electrically connected to two or more memory cells.
    Type: Application
    Filed: November 3, 2021
    Publication date: May 4, 2023
    Inventors: Koichi Motoyama, Hsueh-Chung Chen, CHANRO PARK, Kenneth Chun Kuen Cheng, Chih-Chao Yang
  • SELF-ALIGNED DOUBLE PATTERNING (SADP) INTEGRATION WITH WIDE LINE SPACING
    Publication number: 20230136674
    Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. Mandrels are patterned on a hardmask, where the hardmask is located on an interlayer dielectric layer. Spacers are formed on sidewalls of the mandrels. The mandrels are removed. A wide spacing masking layer is patterned on the interlayer dielectric layer. Exposed portions of the hardmask are etched such that top surfaces of the ILD layer are exposed. Exposed portions of the ILD layer are etched such that a plurality of trenches are formed within the ILD layer. The plurality of trenches are filled with conductive metal.
    Type: Application
    Filed: October 28, 2021
    Publication date: May 4, 2023
    Inventors: Shyng-Tsong Chen, Terry A. Spooner, Koichi Motoyama, Chih-Chao Yang
  • MRAM BOTTOM ELECTRODE SHROUD
    Publication number: 20230137421
    Abstract: A memory device includes a bottom electrode having an uppermost surface, a first sidewall, and a second sidewall. The memory device further includes a dielectric layer covering the uppermost surface and the first and second sidewalls of the bottom electrode such that an uppermost surface of the dielectric layer is arranged higher than the uppermost surface of the bottom electrode. The memory device further includes a metal body in direct contact with the uppermost surface of the bottom electrode and extending through the dielectric layer to the uppermost surface of the dielectric layer. The memory device further includes a memory component arranged in direct contact with the metal body and with the uppermost surface of the dielectric layer.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Oscar van der Straten, Koichi Motoyama, Kenneth Chun Kuen Cheng, Joseph F. Maniscalco, Chih-Chao Yang