Abstract: A semiconductor device is provided. The semiconductor device includes a first source/drain of a first semiconductor device, and a second source/drain of a second semiconductor device. The semiconductor device further includes a source/drain contact adjoining a first side of the first source/drain, a frontside via adjoining the source/drain contact, and a backside electric contact adjoining a first side of the second source/drain, wherein the backside electric contact is on a side opposite the source/drain contact, and a conductive alignment region. The device further includes a backside interconnect electrically connected to the conductive alignment region, wherein the backside interconnect is on the same side of the first and second source/drain as the backside electric contact, and an alignment region via electrically connected to the conductive alignment region, wherein the alignment region via is on the same side of the first and second source/drain as the source/drain contact and frontside via.

Abstract: An integrated circuit (IC) assembly method is provided. The method includes fabricating a first wafer including a first device with a back end of line (BEOL) and first terminals of first and second types at the BEOL and fabricating a second wafer including a second device for back side power delivery network (BSPDN) processing, second terminals of the first type, first vias and second vias. The first and second wafers are bonded at the BEOL to connect the second terminals of the first type to a subset of the first terminals of the first type, the first vias to remaining first terminals of the first type, and the second vias to the first terminals of the second type. A BSPDN is built onto a backside of the second wafer to include first and second BSPDN terminals connected to the first and second vias, respectively.

Abstract: A method of making a semiconductor component includes depositing a first metal material onto a structure having a first cavity and a second cavity such that the first metal material fills the first cavity and forms a first lining on exposed surfaces of the second cavity. The method further includes depositing a dielectric material onto the structure such that the dielectric material forms a second lining on exposed surfaces of the first lining. The method further includes depositing a second metal material onto the structure such that the second metal material fills remaining volume in the second cavity.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes a substrate extending along a first direction to define a length, a second direction orthogonal to the first direction to define a width, and a third direction orthogonal to the first and second direction to define a height. The substrate includes a first capacitance region and a second capacitance region. The first capacitance region has a first maximum operating voltage (Vmax) and the second capacitance region has a second Vmax that is greater than the first Vmax.

Abstract: Embodiments of the invention include a subtractive top via as a bottom electrode contact for an embedded memory structure. Forming the bottom electrode contact includes depositing a conductive material on an underlayer and etching the conductive material to form an extended via and a conductive pad as an integral unit. The extended via extends from the conductive pad such that the extended via is adjacent to a memory structure, the extended via being formed as a first contact for the memory structure.

Abstract: A semiconductor device includes an integrated circuit chip having a frontside and a backside. The frontside includes a frontside signal line configured to transmit signals to a first terminal of a transistor arranged in the integrated circuit chip, and the backside includes a backside power line configured to transmit power to a second terminal of the transistor. The semiconductor device further includes a contact configured to connect a gate of the transistor to a backside signal line configured to transmit signals to the gate of the transistor. The semiconductor device further includes a via extending through the frontside and the backside of the integrated circuit chip. The via is configured to transmit signals between a lowermost contact on the frontside and an uppermost contact on the backside of the integrated circuit chip.

Abstract: Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.

Abstract: A memory device includes a magnetic tunnel junction (MTJ) pillar between a top electrode and a bottom electrode. An amorphous dielectric hardmask is in contact with a first portion of an uppermost surface of the MTJ pillar. A first portion of a metal layer is disposed on opposite sidewalls of the amorphous dielectric hardmask and in contact with a second portion of the uppermost surface of the MTJ pillar extending outwards from the amorphous dielectric hardmask for providing the top electrode. A dielectric underlayer is in contact with a first portion of a bottommost surface of the MTJ pillar, while a second portion of the metal layer is disposed on opposite sidewalls of the dielectric underlayer. The second portion of the metal layer is in contact with a second portion of the bottommost surface of the MTJ pillar extending outwards from the dielectric underlayer for providing the bottom electrode.

Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes patterning a bottom electrode layer and a first ferromagnetic layer on top of the bottom electrode layer; depositing a dielectric layer, the dielectric layer covering the bottom electrode layer and the first ferromagnetic layer; creating an opening in the dielectric layer, the opening exposing a portion of the first ferromagnetic layer; forming a tunnel barrier layer inside the opening; forming a second ferromagnetic layer on top of the tunnel barrier layer; patterning the tunnel barrier layer and the second ferromagnetic layer; and forming a top electrode layer on top of the second ferromagnetic layer. Structures formed thereby are also provided.

Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a magnetic tunnel junction (MTJ) stack; forming a first dielectric layer to a level above a tunnel barrier layer of the MTJ stack, the first dielectric layer partially covering the MTJ stack with a top surface of the MTJ stack being exposed; depositing an etch-stop layer covering the top surface of the MTJ stack and a top surface of the first dielectric layer; depositing a second dielectric layer covering the etch-stop layer; forming an opening in the second dielectric layer; removing a portion of the etch-stop layer above the top surface of the MTJ stack; and forming a top contact by depositing a conductive material in the opening. An MRAM structure formed thereby is also provided.

Abstract: Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming a bottom electrode layer surrounded by a bottom dielectric layer; forming an etch-stop layer on top of the bottom electrode layer and the bottom dielectric layer; creating an opening in the etch-stop layer to expose a top surface of the bottom electrode layer; forming a first ferromagnetic layer on top of the bottom electrode layer and the etch-stop layer, with a portion of the first ferromagnetic layer filling the opening in the etch-stop layer; forming a tunnel barrier layer and a second ferromagnetic layer on top of the first ferromagnetic layer; patterning the second ferromagnetic layer, the tunnel barrier layer, and the first ferromagnetic layer; and forming a top electrode layer on top of the second ferromagnetic layer. A structure formed thereby is also provided.

Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

Abstract: A capping layer is on top of a substrate. A first low-k dielectric layer is on top of the capping layer. One or more trenches are within the first low-k dielectric layer. Each of the one or more trenches have a same depth. Each trench of the one or more trenches include a barrier layer on top of the first low-k dielectric layer, a liner layer and a metal layer on top of the liner layer.

Abstract: The present invention provides a detection chip for quantitative detection of neutralizing antibody and manufacturing method thereof. A sensing layer is disposed on a circuit layer. A shielding layer corresponds a shielding part on the sensing layer to form a sensing area. The surface of the sensing area is hydroxylated to form a self-assembled monolayer film including the aldehyde group. A protein solution is dripped on the sensing area. An external electric field is applied to the sensing layer at an external angle with respect to the normal of the substrate to deflect protein molecules in the protein solution correspondingly. This structure can be applied to rapid and quantitative detection. According to various embodiments of the present invention, the sensing efficiency of the detection chip can be enhanced.

Abstract: A semiconductor component includes an insulative layer having a lowermost surface arranged on top of a bottom dielectric material. The semiconductor component further includes a first interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the first interconnect structure is arranged at a first height relative to the lowermost surface of the insulative layer. The semiconductor component further includes a pillar connected to the first interconnect structure and extending through the insulative layer. The semiconductor component further includes a second interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the second interconnect structure is arranged at a second height relative to the lowermost surface of the insulative layer. The second height is different than the first height.

Abstract: A Resistive Random-Access Memory (RRAM) has an internal electrode; a high k dielectric layer surrounding and in contact with the internal electrode; a lower substrate; and a trench having three or more trench sides disposed within the lower substrate; and one or more interconnects each with an interconnect side. The interconnect side forms part of one of the trench sides. The internal electrode and the high k dielectric layer are disposed within the trench with the interconnect side in contact with the high k dielectric layer. In some embodiments, an external electrode is between and electrically connected to the high k dielectric layer and the internal electrode. The external electrode then forms the electrical connection between the high k dielectric and the interconnect side. Multiple embodiments are disclosed including RRAMs created in multiple substrates; different RRAM configurations; and dual, three-wire RRAMs with two interconnects. Arrays of RRAMs and methods of making are also disclosed.

Abstract: A memory device includes a magnetic tunnel junction pillar located between, and electrically connected to, a bottom electrode and a top electrode. The magnetic tunnel junction pillar is composed of a plurality of device layers vertically stacked above the bottom electrode. Each of the plurality of device layers, the top electrode, and the bottom electrode is formed at a first bevel angle. A bottommost portion of each of the plurality of device layers in the magnetic tunnel junction pillar has a width that is greater than a width of a topmost portion of each preceding device layer. An encapsulation layer is disposed along opposite sidewalls of the top electrode, opposite sidewalls of the bottom electrode, and opposite sidewalls of each of the plurality of device layers.

Abstract: A magnetic tunnel junction (MTJ) stack, where a vertical side surface of a bottom electrode of the MTJ stack is surrounded by an oxide, where the bottom electrode and the oxide are horizontally aligned. A magnetic tunnel junction (MTJ) stack, where a vertical side surface of a bottom electrode of the MTJ stack and a metal spacer below the bottom electrode is surrounded by an oxide, where an upper surface of the bottom electrode is horizontally aligned with a horizontal upper surface of the oxide, where a lower surface of the metal spacer is horizontally aligned with a horizontal lower surface of the oxide. Forming a metal spacer above and vertically aligned with a lower metal line surrounded by a dielectric, and forming a metal layer on the metal spacer and dielectric with a high temperature deposition of the metal layer, where the metal layer oxidizes.

Abstract: A memory device includes a magnetic tunnel junction (MTJ) pillar between a top electrode and a bottom electrode. An amorphous dielectric hardmask is in contact with a first portion of an uppermost surface of the MTJ pillar. A first portion of a metal layer is disposed on opposite sidewalls of the amorphous dielectric hardmask and in contact with a second portion of the uppermost surface of the MTJ pillar extending outwards from the amorphous dielectric hardmask for providing the top electrode. A dielectric underlayer is in contact with a first portion of a bottommost surface of the MTJ pillar, while a second portion of the metal layer is disposed on opposite sidewalls of the dielectric underlayer. The second portion of the metal layer is in contact with a second portion of the bottommost surface of the MTJ pillar extending outwards from the dielectric underlayer for providing the bottom electrode.

Abstract: A magnetic tunnel junction (MTJ) stack, a vertical side surface of the MTJ stack includes a saw tooth edge, the MTJ stack includes vertically aligned layers of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode, the free layer of the MTJ stack has a tapered edge including a first width at an upper portion of the free layer and a second width at a lower portion of the free layer, the first width is greater than the second width. Forming a first bottom electrode of a first MTJ stack, a second bottom electrode of a second MTJ stack, a first inter-layer dielectric between the first and the second bottom electrode, a first reference layer of the first MTJ stack, a second reference layer of the second MTJ stack, a second inter-layer dielectric between the first reference layer and the second reference layer.