Abstract: Embodiments of the invention include a semiconductor structure with a first magneto-resistive random access memory (MRAM) pillar with a bottom electrode layer, a reference layer connected above the bottom electrode layer, a free layer, and a tunnel barrier between the reference layer and the free layer. The MRAM pillar includes a pillar diameter. The semiconductor structure also includes a coaxial top electrode with a top diameter that is less than the pillar diameter.

Abstract: A memory device includes a magnetic tunnel junction pillar extending vertically from a bottom electrode. The magnetic tunnel junction pillar includes a top portion and a bottom portion, the top portion of the magnetic tunnel junction pillar has first opposite sidewalls including a positive taper profile, while the bottom portion of the magnetic tunnel junction has second opposite sidewalls including a negative taper profile. A first encapsulation layer is disposed along the first opposite sidewalls of the top portion of the magnetic tunnel junction pillar, and a second encapsulation layer is disposed along the second opposite sidewalls of the bottom portion of the magnetic tunnel junction pillar. The first and second encapsulation layers can be made of the same or different materials.

Abstract: A memory device includes a magnetic tunnel junction pillar above a bottom electrode. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar with an uppermost surface of the sidewall spacer being coplanar with an uppermost surface of the magnetic tunnel junction pillar. A dielectric hardmask composed of an amorphous dielectric material is disposed above a first portion of the uppermost surface of the magnetic tunnel junction pillar, the dielectric hardmask includes a hemispherical shape. A top electrode is located surrounding the dielectric hardmask and above the uppermost surface of the sidewall spacer and a second portion of the uppermost surface of the magnetic tunnel junction pillar extending outwards from the dielectric hardmask.

Abstract: A method of forming a memory device with a laterally-recessed free layer includes forming a bottom electrode above an electrically conductive structure embedded within an interconnect dielectric material. A magnetic tunnel junction stack is formed above the bottom electrode. Forming the magnetic tunnel junction stack includes forming a magnetic reference layer above the bottom electrode, forming a tunnel barrier layer above the magnetic reference layer, and forming a magnetic free layer above the tunnel barrier layer. Opposed lateral portions of the magnetic free layer are recessed, and sidewall spacers are formed on the recessed opposed lateral portions of the magnetic free layer for confining an active region of the memory device formed by the magnetic free layer and the tunnel barrier layer.

Abstract: A semiconductor device structure includes a memory element disposed within an interlayer dielectric (ILD) layer. A contact is disposed within the ILD in contact with the memory element and includes a first metal. A logic element is disposed within the ILD and comprises a second metal that is different than the first metal. A method of forming the semiconductor structure includes forming at least one memory element within an interlayer dielectric (ILD) layer. A contact that includes a first metal is formed in contact with the memory element. At least one logic element is formed in the ILD layer, where the logic element includes a second metal that is different than the first metal.

Abstract: A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.

Abstract: Embodiments of present invention provide a resistor structure. The resistor structure includes a first layer of electrically insulating material; and a second layer of resistive material directly adjacent to the first layer, wherein thermal conductivity of the first layer is equal to or larger than 100 W/m/K. In one embodiment, the first layer of electrically insulating material has a band gap equal to or larger than 4 eV and is selected from a group consisting of aluminum-nitride (AlN), boron-nitride (BN), and diamond (C).

Abstract: A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.

Abstract: Embodiments of present invention provide a method of forming electrode to a magnetic-tunnel junction device. The method includes providing a supporting structure; depositing a layer of conductive material on top of the supporting structure; performing a first etching of the layer of conductive material to form a connection layer; and performing a second etching of a remaining portion of the layer of conductive material to form a micro-stud, the micro-stud being directly above the connection layer. In one embodiment the supporting structure includes a via opening and the conductive material fills the via opening to form a via.

Abstract: A MRAM Cell including a dielectric cap and a lower section that includes a bottom electrode, a synthetic anti-ferromagnet layer, and a reference layer, where in the sidewalls of each of the bottom electrode, the synthetic anti-ferromagnet layer, and the reference layer are angled relative to the vertical plane perpendicular to a top surface of the dielectric cap. A first dielectric liner located on the sidewalls of each of the lower section. An upper section that includes a tunnel barrier, a free layer, and a top electrode. A second dielectric liner located on a side section of the tunnel barrier, where the second dielectric liner is comprised of a second material, and where the angled side sections of the tunnel barrier are located on top of the second dielectric liner.

Abstract: A semiconductor substrate has a metal via in the substrate, and has, on the substrate, a metal line that is less than 8 nanometers (nm) wide and at least 20 nm tall. A method for making a semiconductor structure includes forming a metal via in a substrate; forming a mandrel atop and offset from the via; depositing a metal-containing liner onto the mandrel; exposing the top of the mandrel by anisotropically etching the liner, thereby defining a separate portion of the liner at each side of the mandrel; and growing a metal line on each portion of the liner.

Abstract: A memory device, and a method of forming the same, includes a bottom electrode above an electrically conductive structure, the electrically conductive structure is embedded in an interconnect dielectric material. A magnetic tunnel junction stack located above the bottom electrode is formed by a magnetic reference layer above the bottom electrode, a tunnel barrier layer above the magnetic reference layer, and a laterally-recessed magnetic free layer above the tunnel barrier layer. Sidewall spacers surround the laterally-recessed magnetic free layer for confining an active region formed by the laterally-recessed magnetic free and the tunnel barrier layer.

Abstract: Forming a vertically stacked interdigitated metal-insulator-metal capacitor includes forming a first set of connecting vias within a first dielectric layer disposed above a semiconductor substrate followed by deposition of a first conductive material above the first dielectric layer, the first conductive material fills the first set of connecting vias. A top portion of the first conductive material is patterned to form a first set of interdigitated electrodes. A remaining portion of the first conductive material below the first set of interdigitated electrodes includes a first metal plate. An insulating layer is conformally deposited above the first conductive material for electrically separating the first set of interdigitated electrodes and the first metal plate.

Abstract: A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.

Abstract: An antifuse structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line, and a conductive etch stop layer separating both the first metal line and the second metal line from an underlying layer, where a first portion of the conductive etch stop layer directly beneath the first metal line comprises a first extension region and a second portion of the conductive etch stop layer directly beneath the second metal line comprises a second extension region opposite the first extension region.

Abstract: Fabrication method for forming a resistance tunable fuse stack structure includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer, a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting at least one of the first and second fuse conductive layers. Selection of various attributes of the fuse stack structure tunes a resistance of a fuse formed between the first and second fuse contacts.

Abstract: Back end of line metallization structures and methods for fabricating self-aligned vias. The structures generally include a first interconnect structure disposed above a substrate. The first interconnect structure includes a metal line formed in a first interlayer dielectric. A second interconnect structure overlies the first interconnect structure. The second interconnect structure includes a second cap layer on the first interlayer dielectric, a second interlayer dielectric thereon, and at least one self-aligned via in the second interlayer dielectric conductively coupled to at least a portion of the metal line of the first interconnect structure, wherein any misalignment of the at least one self-aligned via results in the at least one self-aligned via landing on both the metal line of the first interconnect structure and the second cap layer. The second cap layer is an insulating material.

Abstract: A semiconductor structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line adjacent to the first metal line, a first dielectric contacting sidewalls of the top via, a second dielectric directly between the first dielectric and the second metal line, and an air gap located between the first metal line and the second metal line, and below both the first dielectric and the second dielectric.

Abstract: An integrated circuit structure includes a metal line that has an upper surface defining a periphery; a dielectric spacer that is formed around the periphery of the upper surface of the metal line; and a metal via that contacts the metal line and the dielectric spacer adjacent to the periphery of the upper surface. A method for making a semiconductor structure includes depositing a spacer around the periphery of an upper surface of a metal line; and depositing a via onto the metal line, so that a part of the via overlaps the spacer.

Abstract: An interdigitated metal-insulator-metal capacitor structure is formed by a first unitary body of a first conductive material that includes a first metal plate, a first set of interdigitated electrodes protruding upwards from a top surface of the first metal plate, and a first set of connecting vias protruding downwards from a bottom surface of the first metal plate. A second unitary body of a second conductive material is disposed above the first unitary body and electrically separated from the first unitary body by an insulating layer. The second unitary body includes a second metal plate, a second set of interdigitated electrodes protruding downwards from a bottom surface of the second metal plate, and a second set of connecting vias protruding upwards from a top surface of the second metal plate. The first set of interdigitated electrodes are interleaved with the second set of interdigitated electrodes.