Abstract: The immersion cooling apparatus includes a cooling tank having a cooling liquid; a cable having a first end and a second end and a protection tube wrapping the cable. The first end connects a first connector, and the second end connects a second connector. At least one of the first end and the second end is located in the cooling tank. The protection tube is configured to separate the cable and the cooling liquid, and the protection tube includes at least one of a hard tube, a soft tube, or a thermal shrinking tube.

Abstract: A system and a method for detecting abnormality of a thin-film deposition process are provided. In the method, a thin-film is deposited on a substrate in a thin-film deposition chamber by using a target, a dimension of a collimator mounted between the target and the substrate is scanned by using at least one sensor disposed in the thin-film deposition chamber to derive an erosion profile of the target, and abnormality of the thin-film deposition process is detected by analyzing the erosion profile with an analysis model trained with data of a plurality of erosion profiles derived under a plurality of deposition conditions.

Abstract: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.

Abstract: Exemplary subpixel structures include a directional light-emitting diode structure characterized by a full-width-half-maximum (FWHM) of emitted light having a divergence angle of less than or about 10°. The subpixel structure further includes a lens positioned a first distance from the light-emitting diode structure, where the lens is shaped to focus the emitted light from the light-emitting diode structure. The subpixel structure still further includes a patterned light absorption barrier positioned a second distance from the lens. The patterned light absorption barrier defines an opening in the barrier, and the focal point of the light focused by the lens is positioned within the opening. The subpixels structures may be incorporated into a pixel structure, and pixel structures may be incorporated into a display that is free of a polarizer layer.

Abstract: A method and a kit for detecting Mycobacterium tuberculosis are provided. The method includes a step of performing a nested qPCR assay to a specimen. The nested qPCR assay includes a first round of amplification using external primers and a second round of amplification using internal primers and a probe. The external primers have sequences of SEQ ID NOs. 1 and 2, and the internal primers and the probe have sequences of SEQ ID NOs. 3 to 5.

Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.

Abstract: A multi-shot moulding part structure includes a first structural part, an ink decoration layer, and a second structural part. The first structural part has a first area surface, a second area surface, and a joining surface located on the second area surface. The joining surface is non-parallel to the second area surface. The ink decoration layer is spread on the first area surface and the second area surface, but not on the joining surface. The second structural part is combined with the first structural part and covers the second area surface. The second structural part touches the joining surface. By the second structural part touching the joining surface of the first structural part that is not coated with the ink decoration layer, the structural bonding strength between the first structural part and the second structural part is enhanced.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a field plate, a gate electrode, and a first dielectric layer. The substrate has a top surface. The substrate includes a first drift region with a first conductivity type extending from the top surface of the substrate into the substrate, and includes a second drill region with the first conductivity type extending from the top surface of the substrate into the substrate and adjacent to the first drift region. The field plate is over the substrate. The gate electrode has a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate. The first dielectric layer is between the substrate and the field plate. The first portion of the gate electrode is overlapping with a boundary of the first drift region and the second drift region in the substrate.

Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.

Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.

Abstract: An RF testing method is applied between a testing instrument and multiple devices under test at least including a first DUT and a second DUT. The testing instrument includes a signal generator and a signal analyzer. A sync signal is sent to the testing instrument and the first DUT, so that the first DUT occupies the signal generator to receive a testing signal from the signal generator. The first DUT sends an uplink signal to the signal analyzer based on the testing signal to occupy the signal analyzer for signal analysis at a first point in time. The sync signal is sent to the testing instrument and the second DUT, so that the second DUT occupies the signal generator to receive the testing signal from the signal generator at a second point in time. The first point in time is parallel to the second point in time.

Abstract: The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

Abstract: The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.

Abstract: A method of building a characteristic model includes: acquiring raw electrical data from a measurement system outside one or more processing units; acquiring operational state-related data from an information collector inside the one or more processing units; performing a data annealing process on the raw electrical data and the operational state-related data to obtain and purified electrical data and purified operational state-related data; and performing a machine learning (ML)-based process to build the characteristic model based on the purified electrical data and the purified operational state-related data.

Abstract: A bracket and a terminal equipment are provided. The bracket is provided for a terminal device to be installed thereon and includes a bracket body, two installing elements, and at least one holding element. The two installing elements respectively protrude outward from two sides of the bracket body, and each of the two installing elements includes an engaging portion. The two installing elements are configured to be inserted into the terminal device so the terminal device is installed on the bracket, and each of the engaging portions is configured such that each of the installing elements is engaged with and retained in the terminal device. The holding element protrudes outward from the bracket body and is configured to be inserted into a loading hole of the terminal device.

Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.

Abstract: A powered industrial truck includes a lateral movement assembly including four sliding members and four pivotal members both on a wheeled carriage, four links having a first end pivotably secured to the sliding member and a second end pivotably secured to either end of the pivotal member, a motor shaft having two ends pivotably secured to the pivotal members respectively, a first electric motor on one frame member, and four mounts attached to the sliding members respectively; two lift assemblies including a second electric motor, a shaft having two ends rotatably secured to the sliding members respectively, two gear trains at the ends of the shaft respectively, a first gear connected to the second electric motor, a second gear on the shaft, and a first roller chain on the first and second gears; two electric attachments on the platform and being laterally moveable, each attachment. The mount has rollers.

Abstract: A method for determining a height of a plant, an electronic device, and a storage medium are disclosed. In the method, a target image is obtained by mapping an obtained color image with an obtained depth image. The electronic device processes the color image by using a pre-trained mobilenet-ssd network, obtains a detection box appearance of the plant, and extracts target contours of the plant to be detected from the detection box. The electronic device determines a depth value of each of pixel points in the target contour according to the target image. Target depth values are obtained by performing a de-noising on depth values of the pixel points, and a height of the plant to be detected is determined according to the target depth value. The method improves accuracy of height determination of a plant.