Patents by Inventor Chih Chen

Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948863
    Abstract: A package structure and method of forming the same are provided. The package structure includes a polymer layer, a redistribution layer, a die, and an adhesion promoter layer. The redistribution layer is disposed over the polymer layer. The die is sandwiched between the polymer layer and the redistribution layer. The adhesion promoter layer, an oxide layer, a through via, and an encapsulant are sandwiched between the polymer layer and the redistribution layer. The encapsulant is laterally encapsulates the die. The through via extends through the encapsulant. The adhesion promoter layer and the oxide layer are laterally sandwiched between the through via and the encapsulant. A bottom portion of the encapsulant is longitudinally sandwiched between the adhesion promoter layer and the polymer layer.
    Type: Grant
    Filed: February 8, 2023
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Wei-Chih Chen
  • Patent number: 11948904
    Abstract: A die includes a substrate, a conductive pad, a connector and a protection layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector includes a seed layer and a conductive post. The protection layer laterally covers the connector. Topmost surfaces of the seed layer and the conductive post and a top surface of the protection layer are level with each other.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 11948938
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
  • Patent number: 11948920
    Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Chun Hsu, Yan-Zuo Tsai, Chia-Yin Chen, Yang-Chih Hsueh, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 11947818
    Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: writing data into a plurality of pages of a specific block, and establishes or updates a F2H mapping table based on physical addresses of the plurality of pages and logical addresses of the data; using the F2H mapping table to update a H2F mapping table; initializing a flush-bitmap, wherein the flush-bitmap records a plurality of flush bits corresponding to the physical addresses of the plurality of pages, respectively; receiving a trim command from a host device, wherein the trim command asks to mark at least one of the logical addresses of the data as invalid; updating the H2F mapping data according to the trim command; updating the flush-bitmap according to the trim command; and writing the updated H2F mapping table and the updated flush-bitmap into the flash memory module.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: April 2, 2024
    Assignee: Silicon Motion, Inc.
    Inventors: Ching-Ke Chen, Wei-Chih Hsu
  • Patent number: 11950307
    Abstract: This document describes techniques and devices for efficient handling of a resource control state change and multi-node connectivity. Instead of performing multiple radio resource control (RRC) procedures to change a resource control state of a user equipment (UE) and establish, modify, or release a connection with multi-node connectivity, the techniques described herein combine the multiple RRC procedures into a single RRC procedure that supports both a resource control state change and multi-node connectivity. In particular, a master node sends a resource control state and multi-node connectivity message that includes both state change information and multi-node connectivity information. With this single message, timing and power resources of the UE can be conserved and failures resulting from asynchronous communication of the state change information and the multi-node connectivity information can be avoided.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: April 2, 2024
    Assignee: Google LLC
    Inventors: Chih-Hsiang Wu, Teming Chen
  • Publication number: 20240100743
    Abstract: A separation apparatus suitable for separating plastic and silicone in a composite material includes a storage tank configured to store a hydrocarbon solvent, and a reaction tank fluidly connected to the storage tank and having a reaction space for placement of the composite material therein and for receiving the hydrocarbon solvent from the storage tank such that the composite material is immersed in the hydrocarbon solvent for separating the plastic and the silicone in the composite material. The plastic and the silicone in the composite material are insoluble in the hydrocarbon solvent.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 28, 2024
    Applicants: Taiwan Green Point Enterprises Co., Ltd., Jabil Circuit (Singapore) Pte. Ltd.
    Inventors: Bing-Yuan Lin, Ying-Yin Chen, Yung-Chih Chen, Ching-Hsin Chen
  • Publication number: 20240102742
    Abstract: A liquid-cooled cooling structure includes a cooling main body having a condensation chamber and an evaporation chamber arranged vertically therein; a separation member arranged between and separating the condensation chamber and the evaporation chamber, and having a first through hole and a second through hole communicating with the condensation chamber and the evaporation chamber, a dimension of the first through hole being greater than that of the second through hole; a longitudinal partition board received in the condensation chamber and arranged between the first through hole and the second through hole and separating the condensation chamber into a first channel and a second channel; cooling fins extended from an outer perimeter of the cooling main body.
    Type: Application
    Filed: September 25, 2022
    Publication date: March 28, 2024
    Inventors: Yen-Chih CHEN, Chi-Fu CHEN, Wei-Ta CHEN, Hung-Hui CHANG
  • Publication number: 20240104809
    Abstract: Embodiments described herein provide systems and methods for multimodal layout generations for digital publications. The system may receive as inputs, a background image, one or more foreground texts, and one or more foreground images. Feature representations of the background image may be generated. The foreground inputs may be input to a layout generator which has cross attention to the background image feature representations in order to generate a layout comprising of bounding box parameters for each input item. A composite layout may be generated based on the inputs and generated bounding boxes. The resulting composite layout may then be displayed on a user interface.
    Type: Application
    Filed: January 30, 2023
    Publication date: March 28, 2024
    Inventors: Ning Yu, Chia-Chih Chen, Zeyuan Chen, Caiming Xiong, Juan Carlos Niebles Duque, Ran Xu, Rui Meng
  • Publication number: 20240105805
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes channel structures vertically stacked over a substrate and a source/drain structure laterally attached to the channel structures in the first direction. The semiconductor structure also includes a dielectric wall structure laterally attached to the channel structures in the second direction. The second direction is different from the first direction. In addition, the dielectric wall structure includes a bottom portion and a cap layer formed over the bottom portion. The semiconductor structure also includes an isolation feature vertically overlapping the cap layer of the dielectric wall structure and a gate structure formed around the channel structures and covering a sidewall of the isolation feature.
    Type: Application
    Filed: February 2, 2023
    Publication date: March 28, 2024
    Inventors: Chun-Sheng LIANG, Hong-Chih CHEN, Ta-Chun LIN, Shih-Hsun CHANG, Chih-Hao CHANG
  • Publication number: 20240105480
    Abstract: A wafer storage elevator and method for detecting wafer position shift. The elevator includes a first storage elevator sidewall, a second storage elevator sidewall, and a storage seat positioned between the first and second storage elevator sidewalls. A first mirror block is coupled to a front side of the storage seat having a mirror positioned on a top surface of the block, and a second mirror block is coupled to the front side of the storage seat having a mirror that is positioned on the top surface of the second mirror block. The mirror of the first mirror block reflects a laser beam from an emission sensor to the second mirror block, and the mirror of the second mirror block reflects the laser beam from the mirror of the first mirror block to a receive sensor. A wafer misalignment is determined based upon an output of the receive sensor.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 28, 2024
    Inventors: Ming-Sze Chen, Yuan-Hsin Chi, Hung-Chih Wang, Sheng-Yuan Lin
  • Publication number: 20240105786
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain (S/D) region disposed over a substrate, a second S/D region disposed over the substrate, a dielectric wall disposed between the first and second S/D regions, a first conductive contact disposed over and electrically connected to the first S/D region, a second conductive contact disposed over and electrically connected to the second S/D region, and a first dielectric material in contact with the dielectric wall. The first dielectric material has a top surface located at a first level between a top surface of the first conductive contact and a bottom surface of the first conductive contact, and the first dielectric material extends from the first level to a second level located below the bottom surface of the first conductive contact.
    Type: Application
    Filed: January 15, 2023
    Publication date: March 28, 2024
    Inventors: Chun-Sheng LIANG, Hong-Chih CHEN
  • Publication number: 20240100352
    Abstract: A phototherapy device includes a base, at least one light conversion device and a light source module. The base has an installation slot. The light conversion device is detachably arranged in the installation slot. Each light conversion device includes a plurality of light conversion patterns. The light source module is arranged on a side of the base and configured to provide an excitation beam to the light conversion patterns, so that each of the light conversion patterns emits a converted beam. In this way, the light conversion device of the phototherapy device can be replaced according to the user's needs.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 28, 2024
    Inventors: CHUNG-JEN OU, YU-MIN CHEN, MING-WEI TSAI, CHIEN-CHIH CHEN
  • Patent number: 11940388
    Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 26, 2024
    Assignee: IXENSOR CO., LTD.
    Inventors: Yenyu Chen, An Cheng Chang, Tai I Chen, Su Tung Yang, Chih Jung Hsu, Chun Cheng Lin, Min Han Wang, Shih Hao Chiu
  • Patent number: 11941741
    Abstract: A graphics system includes an effect engine and a graphics pipeline. The graphics pipeline performs pipeline operations on graphical objects in a frame. The graphics pipeline includes at least a fragment shader stage. An application programming interface (API) provides an instruction that specifies a subset of the graphical objects in the frame for the effect engine to execute. When detecting the instruction, the graphics pipeline invokes the effect engine to perform a predefined set of graphics operations on the subset of the graphical objects in the frame. The predefined set of graphics operations has a higher computational complexity than the pipeline operations.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: March 26, 2024
    Assignee: MediaTek Inc.
    Inventors: Chien-Chih Wang, Ying-Chieh Chen
  • Patent number: 11941873
    Abstract: In various examples, sensor data may be received that represents a field of view of a sensor of a vehicle located in a physical environment. The sensor data may be applied to a machine learning model that computes both a set of boundary points that correspond to a boundary dividing drivable free-space from non-drivable space in the physical environment and class labels for boundary points of the set of boundary points that correspond to the boundary. Locations within the physical environment may be determined from the set of boundary points represented by the sensor data, and the vehicle may be controlled through the physical environment within the drivable free-space using the locations and the class labels.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: March 26, 2024
    Assignee: NVIDIA Corporation
    Inventors: Mansi Rankawat, Jian Yao, Dong Zhang, Chia-Chih Chen
  • Patent number: 11942509
    Abstract: A light-emitting device comprises a substrate; a first light-emitting unit and a second light-emitting unit formed on the substrate, each of the first light-emitting unit and the second light-emitting unit comprises a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the first light-emitting unit comprises a first semiconductor mesa and a first surrounding part surrounding the first semiconductor mesa, and the second light-emitting unit comprises a second semiconductor mesa and a second surrounding part surrounding the second semiconductor mesa; a trench formed between the first light-emitting unit and the second light-emitting unit and exposing the substrate; a first insulating layer comprising a first opening on the first surrounding part and a second opening on the second semiconductor layer of the second light-emitting unit; and a connecting electrode comprising a first connecting part on the first
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: March 26, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, I-Lun Ma, Bo-Jiun Hu, Yu-Ling Lin, Chien-Chih Liao
  • Patent number: 11942941
    Abstract: A device including a first supply voltage track, a second supply voltage track, a first reference track, a first standard cell, and a second standard cell. The first supply voltage track is configured to provide a first voltage and the second supply voltage track is configured to provide a second voltage that is greater than the first voltage. The first standard cell is configured to be electrically connected to the first supply voltage track to receive the first voltage and electrically connected to the first reference track. The second standard cell is configured to be electrically connected to the second supply voltage track to receive the second voltage and electrically connected to the first reference track.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chih Ou, Wen-Hao Chen
  • Patent number: 11937932
    Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: March 26, 2024
    Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITY
    Inventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
  • Patent number: 11941410
    Abstract: Systems and methods for generating, distributing, and using performance mode BIOS configurations are disclosed. Each performance mode BIOS configuration can be a unique set of BIOS setting values that have been established to optimize a particular performance parameter or set of performance parameters, such as boot speed or operating system installation speed. Based on a given hardware configuration and/or set of performance parameters, one or more performance mode BIOS configurations can be packaged and transferred to a memory of a BMC in the form of one or more configuration payloads. The BIOS Setup Utility can display all configuration payloads, such as listed by the type of performance mode (e.g., “Boot Speed Performance Mode” and “OS Installation Performance Mode”), that are available in the BMC memory and allow a user to overwrite the memory containing the current BIOS configuration with a selected configuration payload.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: March 26, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Lung-Chih Chen, Tian-You Chen, Ting-Wei Chien, Chao-Kai Huang