Patents by Inventor Chih-Chieh (Steve) Wang

Chih-Chieh (Steve) Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11418223
    Abstract: The present disclosure provides a dual-band transformer structure, which is suitable for at least two frequencies. The dual-band transformer structure includes a metal layer, a first transmission line, a second transmission line, and a third transmission line. The first transmission line and the second transmission line are disposed on the metal layer. A first end of the second transmission line is coupled to a second end of the first transmission line. A second end of the second transmission line is aligned with an edge of the metal layer, and a first end of the third transmission line is coupled to the second end of the second transmission line. The third transmission line extends away from the edge.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: August 16, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Tzu-Hao Hsieh, Chih-Chieh Wang
  • Patent number: 11417377
    Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chieh Chiu, Chia-En Huang, Fu-An Wu, I-Han Huang, Jung-Ping Yang
  • Patent number: 11417566
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Hao Kung, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Publication number: 20220254747
    Abstract: A semiconductor package includes an interconnect structure, an insulating layer and a conductive layer. The interconnect structure includes a first surface and a second surface opposite to the first surface. The insulating layer contacts the interconnect structure. The insulating layer includes a third surface contacting the second surface of the interconnect structure and a fourth surface opposite to the third surface. The conductive layer is electrically coupled to the interconnect structure. The conductive layer has a continuous portion extending from the second surface to the fourth surface.
    Type: Application
    Filed: April 26, 2022
    Publication date: August 11, 2022
    Inventors: CHUEI-TANG WANG, CHIH-CHIEH CHANG, YU-KUANG LIAO, HSING-KUO HSIA, CHIH-YUAN CHANG, JENG-SHIEN HSIEH, CHEN-HUA YU
  • Patent number: 11399436
    Abstract: A circuit board includes a baseboard, a first conductive circuit layer, a second conductive circuit layer, at least one through hole, and a number of conductive lines. The first conductive circuit layer includes a number of first conductive circuit lines formed on a first side of the baseboard. The second conductive circuit layer includes a number of second conductive circuit lines formed on a second side of the baseboard. The through hole is defined through the first conductive circuit layer, the baseboard, and the second conductive circuit layer. The number of conductive lines are formed in an inner wall of the through hole and spaced apart around the through hole. Each conductive line electrically couples one of the first conductive circuit lines to a corresponding one of the second conductive circuit lines.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: July 26, 2022
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventor: Chih-Chieh Fu
  • Publication number: 20220230674
    Abstract: An operation method for a memory device is provided. The operation method includes: increasing an adjacent word line voltage to a first adjacent word line voltage during a pre-turn on period; and increasing the adjacent word line voltage from the first adjacent word line voltage to a second adjacent word line voltage after the pre-turn on period is finished; wherein the first adjacent word line voltage is lower than the second adjacent word line voltage; the adjacent word line voltage is applied to at least one adjacent word line, and the at least one adjacent word line is adjacent to a selected word line.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 21, 2022
    Inventors: Chih-Chieh CHENG, Chun-Chang LU, Wen-Jer TSAI
  • Publication number: 20220231654
    Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability.
    Type: Application
    Filed: February 11, 2022
    Publication date: July 21, 2022
    Inventors: Emre Ayranci, Miles Sanner, Ke Li, James Francis McElwee, Tero Tapio Ranta, Kevin Roberts, Chih-Chieh Cheng
  • Publication number: 20220230702
    Abstract: A computer-implemented method for executing a computation task in a molecular dynamic simulation includes identifying a bonding target on a ligand; constructing a protein structure; rendering an image of the ligand; subsampling data pertaining to the constructed protein structure and the image of the ligand at a particular frequency; rendering a two-dimensional image of the constructed protein structure relative to the ligand from a plurality of viewpoints; computing optical flows of the protein structure relative to the ligand based on the two-dimensional image; analyzing the optical flows to determine a displacement of atoms; simulating a binding state outcome of the protein structure relative to the ligand for each of the plurality of viewpoints; and predicting a probability of the protein structure binding with the ligand, based on the predicted binding state outcome for each of the plurality of viewpoints.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 21, 2022
    Inventors: Giacomo Domeniconi, Leili Zhang, Guojing Cong, Chih-Chieh Yang, Ruhong Zhou
  • Publication number: 20220231030
    Abstract: A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Chao-Ching Cheng, Tzu-Chiang Chen, Chih-Chieh Yeh
  • Publication number: 20220220535
    Abstract: Provided are compositions and methods for identifying a specific strain of Lactobacillus plantarum, e.g., Lactobacillus plantarum subsp. plantarum PS128 deposited under DSMZ Accession No. DSM 28632.
    Type: Application
    Filed: January 13, 2021
    Publication date: July 14, 2022
    Applicant: BENED BIOMEDICAL CO., LTD.
    Inventors: Ying-Chieh TSAI, Chien-Chen WU, Chih-Chieh HSU
  • Patent number: 11385267
    Abstract: A power detector with wide dynamic range. The power detector includes a linear detector, followed by a voltage-to-current-to-voltage converter, which is then followed by an amplification stage. The current-to-voltage conversion in the converter is performed logarithmically. The power detector generates a desired linear-in-dB response at the output. In this power detector, the distribution of gain along the signal path is optimized in order to preserve linearity, and to minimize the impact of offset voltage inherently present in electronic blocks, which would corrupt the output voltage. Further, the topologies in the sub-blocks are designed to provide wide dynamic range, and to mitigate error sources. Moreover, the temperature sensitivity is designed out by either minimizing temperature variation of an individual block such as the v-i-v detector, or using two sub-blocks in tandem to provide overall temperature compensation.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: July 12, 2022
    Assignee: pSemi Corporation
    Inventors: Damian Costa, Chih-Chieh Cheng, Christopher C. Murphy, Tero Tapio Ranta
  • Publication number: 20220216301
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20220216330
    Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Inventors: Zi-Ang Su, Ming-Shuan Li, Chih Chieh Yeh
  • Publication number: 20220209146
    Abstract: A flexible display module includes a first light-transmissive layer and a first display layer. The first light-transmissive layer includes a display surface. The first light-transmissive layer has a first width in a second direction. The first display layer is disposed below the first light-transmissive layer. The first display layer has a second width in the second direction. The first display layer includes a circuit layer. The flexible display module is configured to be bent along an axis, the axis extends along a first direction, the first direction is perpendicular to the second direction, and the first width is greater than the second width. A line width of the circuit layer more close to a periphery of the display surface is less than a line width of the circuit layer more close to an inner area of the display surface.
    Type: Application
    Filed: November 4, 2021
    Publication date: June 30, 2022
    Inventors: Ming-Chang HSU, Chih-Chieh LIN, Ming-Hsuan YU, Ming-Wei LIN
  • Publication number: 20220208533
    Abstract: A surface processing equipment using energy beam including a multi-axis platform, a surface profile measuring device, an energy beam generator and a computing device is provided. The multi-axis platform is configured to carry a workpiece and move the workpiece to the first position or the second position. The surface profile measuring device has a working area, and the first position is located on the working area. The surface profile measuring device is configured to measure the workpiece to obtain surface profile. The energy beam generator is configured to provide an energy beam to the workpiece for processing, and the second position is located on a transmission path of the energy beam. The computing device is connected to the surface profile measuring device and the energy beam generator. The computing device adjusts the energy beam generator according to the error profile.
    Type: Application
    Filed: December 26, 2020
    Publication date: June 30, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Chieh Chen, Chih-Chiang Weng, Yo-Sung Lee
  • Publication number: 20220202990
    Abstract: A tissue scaffold for use in a tendon and/or ligament is provided, which includes a weave formed by interlacing warp yarns and weft yarns, wherein the warp yarns include a plurality of fibers with an alternative shaped cross section structure, and the weave includes: a main body area with a bioactive component formed on the fiber surface, and a fixed area comprises the weft yarn having a bioceramic material. The tissue scaffold prepared in the present disclosure has the characteristics of stimulating the growth of tissues and inducing tissue repair, effectively improving the ability of tissue regeneration and bone healing, and is beneficial to the reconstruction of the tendon and/or ligament.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Inventors: Hsin-Hsin Shen, Pei-I Tsai, Chih-Chieh Huang, Chien-Cheng Tai, Yi-Hung Wen, Jeng-Liang Kuo, Chun-Hsien Ma, Lih-Tao Hsu, Shin-I Huang, Kuo-Yi Yang, Tsung-Hsien Wu
  • Patent number: 11373879
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Grant
    Filed: September 12, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Kai Chen, Ching-Hsiang Tsai, Kao-Feng Liao, Chih-Chieh Chang, Chun-Hao Kung, Fang-I Chih, Hsin-Ying Ho, Chia-Jung Hsu, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 11375619
    Abstract: A packaging structure, includes: a dielectric layer; at least one inner wiring layer embedded in the dielectric layer; at least two outer wiring layers arranged two sides of the at least one inner wiring layer and combined with the dielectric layer; and at least one electronic component embedded in the dielectric layer; each inner wiring layer including at least two spaced supporting pads, and each supporting pad including a main body and a protruding portion extending outward from a periphery of the main body, the packaging structure further including at least two spaced positioning pillars, and each positioning pillar correspondingly connected to one main body, each electronic component arranged between at least two positioning pillars, and an end of each electronic component being in contact with protruding portions of at least two supporting pads, thereby packaging the electronic component accurately. The present invention also needs to provide a method for manufacturing the packaging structure.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: June 28, 2022
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventor: Chih-Chieh Fu
  • Publication number: 20220187056
    Abstract: A measuring equipment, applied to carry a workpiece to be measured, includes a main base and a positioning device. The main base includes a measuring center axis. The positioning device includes at least two positioning elements. Each of the at least two positioning elements is disposed movably on the main base, and each of the at least two positioning elements is moved with respect to the measuring center axis. An identical distance is there from each of the at least two positioning elements to the measuring center axis. Each of the at least two positioning elements is used for the workpiece to contact and to be positioned to the measuring center axis.
    Type: Application
    Filed: July 7, 2021
    Publication date: June 16, 2022
    Inventors: YI-CHENG CHEN, YI-CHIA HSU, CHIA-CHING LIN, CHIH-CHIEH CHAO
  • Patent number: 11362077
    Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chuei-Tang Wang, Hsing-Kuo Hsia, Chen-Hua Yu