Patents by Inventor Chih-Chieh (Steve) Wang

Chih-Chieh (Steve) Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11612624
    Abstract: This disclosure provides a method of protecting a subject for exercise that prevents an exercise-related harmful effect and reducing exercise fatigue in the subject to thereby enhance physical performance and promote anti-fatigue and anti-inflammatory effects in the subject.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: March 28, 2023
    Assignee: BENED BIOMEDICAL CO., LTD.
    Inventors: Ying-Chieh Tsai, Kuo-Wei Tseng, Chih-Chieh Hsu, Chien-Chen Wu
  • Publication number: 20230078573
    Abstract: A planarization method includes: providing a substrate, wherein the substrate includes a first region and a second region having different degrees of hydrophobicity or hydrophilicity, the second region covering an upper surface of the first region; polishing the substrate with a polishing slurry until the upper surface of the first region is exposed; and continuing polishing and performing a surface treatment by the polishing slurry to adjust the degree of hydrophobicity or hydrophilicity of at least one of the first region and the second region. The polishing slurry and the upper surface of the second region have a first contact angle, and the polishing slurry and the upper surface of the first region have a second contact angle. The surface treatment keeps a contact angle difference between the first contact angle and the second contact angle being equal to or less than 30 degrees during the polishing.
    Type: Application
    Filed: June 23, 2022
    Publication date: March 16, 2023
    Inventors: TUNG-KAI CHEN, CHING-HSIANG TSAI, KAO-FENG LIAO, CHIH-CHIEH CHANG, CHUN-HAO KUNG, FANG-I CHIH, HSIN-YING HO, CHIA-JUNG HSU, HUI-CHI HUANG, KEI-WEI CHEN
  • Patent number: 11605622
    Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chuei-Tang Wang, Hsing-Kuo Hsia, Chen-Hua Yu
  • Publication number: 20230071502
    Abstract: A dual-band transform circuit structure includes a first transmission line, a second transmission line, and a conductive layer. The first transmission line has a first input terminal, a first output terminal, and a second output terminal. The second transmission line has a second input terminal, a third input terminal, a third output terminal, and a fourth output terminal. The second input terminal is coupled to the first output terminal, and the third input terminal is coupled to the second output terminal. The conductive layer is stacked with the first transmission and the second transmission line. The conductive layer includes a first hollow pattern. The first hollow pattern and the second transmission line are overlapped in a top view.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 9, 2023
    Inventors: TZU-HAO HSIEH, CHIH-CHIEH WANG
  • Publication number: 20230073231
    Abstract: The purpose of the present invention is to provide an information processing device capable of executing a quantum program, including: a support vector decision unit that decides a support vector from among a plurality of pieces of teacher data; and a classification execution unit that classifies target data into a plurality of classes on the basis of the support vector, wherein the classification execution unit classifies the target data on the basis of results of time evolution computation of an energy level in the case where the target data is treated as an Ising model.
    Type: Application
    Filed: January 22, 2021
    Publication date: March 9, 2023
    Inventors: Masaru Sogabe, Tomah Sogabe, Chih-chieh Chen, Kodai Shiba
  • Patent number: 11600339
    Abstract: An operation method for a memory device is provided. The operation method includes: increasing a dummy word line voltage to a first dummy word line voltage during a pre-tum on period; increasing the dummy word line voltage from the first dummy word line voltage to a second dummy word line voltage during a read period; and lowering the dummy word line voltage after the read period is finished. Wherein the first dummy word line voltage is lower than the second dummy word line voltage.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: March 7, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Chieh Cheng, Chun-Chang Lu, Wen-Jer Tsai
  • Patent number: 11600719
    Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zi-Ang Su, Ming-Shuan Li, Chih Chieh Yeh
  • Patent number: 11596450
    Abstract: A low-profile offset-type spinal fusion device includes a first screw, a connection base, a nut and a compression part. The first screw has an external thread and a flange. The connection base includes a penetration part and a connection part disposed no higher than the penetration part, and can sleeve the first screw through a first hole of the penetration part to contact the flange with opposite ends of the first screw protruding out of the first hole. The nut, used to engage the first screw, has a bottom surface to contact against the penetration part. When the first screw is installed by penetrating the first hole, the nut and the flange are located to opposite ends of the first hole. The compression part is to screw into a cavity of the connection part for depressing a connecting bar tightly in the cavity.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 7, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Hsin Shen, Pei-I Tsai, Chih-Chieh Huang, Kuo-Yi Yang, Yi-Hung Wen, Wei-Lun Fan, Fang-Jie Jang, Shih-Ping Lin
  • Publication number: 20230064918
    Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: CHUN-WEI HSU, CHIH-CHIEH CHANG, YI-SHENG LIN, JIAN-CI LIN, JENG-CHI LIN, TING-HSUN CHANG, LIANG-GUANG CHEN, JI CUI, KEI-WEI CHEN, CHI-JEN LIU
  • Publication number: 20230069501
    Abstract: A method includes providing a first semiconductor layer at a frontside of a structure; implanting first dopants of a first conductivity-type into the first semiconductor layer, resulting in a doped layer in the first semiconductor layer; forming a stack of semiconductor layers over the first semiconductor layer; patterning the stack of semiconductor layers and the first semiconductor layer into fins; forming an isolation structure adjacent to a lower portion of the fins; etching the stack of semiconductor layers to form a source/drain trench over the first semiconductor layer; forming a source/drain feature in the source/drain trench, wherein the source/drain feature is doped with second dopants of a second conductivity-type opposite to the first conductivity-type; forming a contact hole at a backside of the structure, wherein the contact hole exposes the doped layer in the first semiconductor layer; and forming a first contact structure in the contact hole.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Chih Chieh Yeh, Ming-Shuan Li, Chih-Hung Wang, Zi-Ang Su
  • Publication number: 20230064001
    Abstract: A device includes a diffraction-based overlay (DBO) mark having an upper-layer pattern disposed over a lower-layer pattern, and having smallest dimension greater than about 5 micrometers. The device further includes a calibration mark having an upper-layer pattern disposed over a lower-layer pattern, positioned substantially at a center of the DBO mark, and having smallest dimension less than about 1/5 the size of the smallest dimension of the DBO mark.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Hung-Chung CHIEN, Chih-Chieh YANG, Hao-Ken HUNG, Ming-Feng SHIEH
  • Publication number: 20230057702
    Abstract: Semiconductor device includes light-emitting die and semiconductor package. Light emitting die includes substrate and first conductive pad. Substrate has emission region located at side surface. First conductive pad is located at bottom surface of substrate. Semiconductor package includes semiconductor-on-insulator substrate, interconnection structure, second conductive pad, and through semiconductor via. Semiconductor-on-insulator substrate has linear waveguide formed therein. Interconnection structure is disposed on semiconductor-on-insulator substrate. Edge coupler is embedded within interconnection structure and is connected to linear waveguide. Semiconductor-on-insulator substrate and interconnection structure include recess in which light-emitting die is disposed. Edge coupler is located close to sidewall of recess. Second conductive pad is located at bottom of recess. Through semiconductor via extends across semiconductor-on-insulator substrate to contact second conductive pad.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 11575351
    Abstract: An improved architecture for a radio frequency (RF) power amplifier, impedance matching network, and selector switch. One aspect of embodiments of the invention is splitting the functionality of a final stage impedance matching network (IMN) into two parts, comprising a base set of off-chip IMN components and an on-chip IMN tuning component. The on-chip IMN tuning component may be a digitally tunable capacitor (DTC). In one embodiment, an integrated circuit having a power amplifier, an on-chip IMN tuner, and a selector switch is configured to be coupled to an off-chip set of IMN components. In another embodiment, an integrated circuit having an on-chip IMN tuner and a selector switch is configured to be coupled through an off-chip set of IMN components to a separate integrated circuit having an RF power amplifier.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: February 7, 2023
    Assignee: pSemi Corporation
    Inventors: Tero Tapio Ranta, Chih-Chieh Cheng, Kevin Roberts
  • Publication number: 20230035179
    Abstract: A display panel and a spliced display are provided. The display panel includes a substrate, a plurality of light-emitting elements, a driving circuit, and an optical sensor. The substrate includes a through hole, and the through hole includes a hole. The plurality of the light-emitting elements are disposed on the substrate. The through hole is located in a region between two of the plurality of the light-emitting elements. The driving circuit is disposed on the substrate and electrically connected to the plurality of the light-emitting elements. The optical sensor is disposed corresponding to the through hole and receives sensing light through the hole. The width W of the hole meets the equation of H?W<D. H is the depth of the hole, and D is the distance between the two of the plurality of the light-emitting elements.
    Type: Application
    Filed: October 7, 2022
    Publication date: February 2, 2023
    Applicant: Innolux Corporation
    Inventors: Chin-Lung Ting, Chien-Chih Chen, Ti Chung Chang, Chih-Chieh Wang, Jenhung Li
  • Patent number: 11569130
    Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a material layer formed over the fin structure. The material layer and the isolation structure are made of different materials, the material layer has a top surface with a top width and a bottom surface with a bottom width, and the bottom width is greater than the top width.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Chih-Chieh Yeh
  • Patent number: 11567516
    Abstract: A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: January 31, 2023
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventors: Ching-Hsiang Chang, Chih-Chieh Yao, Chun-Hsiang Lai
  • Publication number: 20230010087
    Abstract: The present disclosure provides a memory array. The memory array includes a first memory cell, a first word line, a second word line, a first bit line, a first complementary bit line, a second bit line, a second complementary bit line, a first sense amplifier, a second sense amplifier and a first logic circuit. When the memory array operates in a binary content-addressable memory (BCAM) mode, during a search operation, a first logic output indicates whether a logic level of the first word line matches a first logic value at a first terminal of a first data storage of the first memory cell, and whether a logic level of the second word line matches a first complementary logic value at a second terminal of the first data storage of the first memory cell.
    Type: Application
    Filed: November 10, 2021
    Publication date: January 12, 2023
    Inventors: Chun-Heng CHEN, Chun-Yen LIN, Chih-Chieh CHIU
  • Publication number: 20230011276
    Abstract: A memory device includes a pair of memory cells, an analog-to-digital converter (ADC), and a processing circuit. The pair of memory cells has a first memory cell and a second memory cell. The ADC, having a first input terminal and a second input terminal, is configured to convert a first data signal at the first input terminal and a second data signal at the second input terminal into a digital output indicating a data value associated with a particular state stored in the pair of memory cells. The processing circuit, coupled to a storage node of the first memory cell, a storage node of the second memory cell, and the first and the second input terminals, is configured to selectively adjust the first data signal and the second data signal according to first data stored in the first memory cell and second data stored in the second memory cell.
    Type: Application
    Filed: December 27, 2021
    Publication date: January 12, 2023
    Inventors: Chih-Chieh CHIU, Chun-Yen LIN, Chih-Lung CHEN
  • Patent number: 11549667
    Abstract: A lighting device includes a housing, a light emitting module, a press plate and a fixing member. The housing has a bottom plate, a base and multiple stopping portions. The base protrudes from the bottom plate, and has a top surface and an inclined surface. The stopping portions are arranged at the bottom plate and extend to a bottom portion of the inclined surface of the base. The light emitting module includes a light panel and multiple light emitting elements arranged thereon. The light panel leans on the inclined surface and stopped by the stopping portions. The press plate is located at the top surface, and presses against the light panel. The fixing member fixes the press plate at the top surface to cause the press plate to press the light panel downward, so as to fix the light panel on the inclined surface.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: January 10, 2023
    Assignee: JULUEN ENTERPRISE CO., LTD.
    Inventors: Chao-Ching Liu, Jen-Hao Cheng, Chih-Chieh Lu
  • Publication number: 20230005513
    Abstract: The present application discloses an interface transformer. The interface transformer includes a first clock generator, a combinational circuit, and a second clock generator. The first clock generator generates an intermediate clock signal according to an input clock signal. A rising edge of the input clock signal precedes a rising edge of the intermediate clock signal, and a falling edge of the intermediate clock signal precedes a falling edge of the input clock signal. The combinational circuit generates a mask clock signal by delaying the intermediate clock signal. The second clock generator generates a transformed clock signal according to the input clock signal and the mask clock signal. The transformed clock signal has two pulses within a cycle of the input clock signal.
    Type: Application
    Filed: October 14, 2021
    Publication date: January 5, 2023
    Inventors: I-HAN HUANG, CHIH-CHIEH CHIU