Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

Abstract: An electronic device is provided. The electronic device includes a supporting substrate, a flexible substrate disposed on the supporting substrate, a first conductive layer disposed on the flexible substrate, a second conductive layer disposed on the first conductive layer, a plurality of organic elements disposed between the first conductive layer and the second conductive layer, and an opening passing through the supporting substrate and exposing a portion of the flexible substrate. The first conductive layer alternately contacts the second conductive layer and the plurality of organic elements.

Abstract: A pogo pin-free testing device for IC chip test includes a load board, a ceramic interposer disposed on the load board, and copper core balls. The ceramic interposer has first and second surfaces and connecting points, and the second surface of the ceramic interposer faces the load board. Each connecting point has through holes penetrating the first and second surfaces, and an inner sidewall surface thereof has a metallization layer. The metallization layer is extended to a portion of the first surface and a portion of the second surface. In each of the connecting points, an area of an extending portion of the metallization layer extended to the second surface is less than an area of an extending portion of the metallization layer extended to the first surface. The copper core balls are disposed between the load board and the through holes of each connecting point of the ceramic interposer.

Abstract: A polish pad replacing apparatus includes a polish spindle loaded with a first polish pad, a first roller movable reciprocally under the polish spindle, a clamping element and a position sensor. The clamping element, disposed at the first roller, is to clamp or release the first polish pad. In replacing the first polish pad, a controller moves the polish spindle to a replacing position, the position sensor detects the polish spindle and if positive, have the controller to moves the first roller to insert the clamping element between the polish spindle and the first polish pad so as to clamp an edge of the first polish pad, the first roller is then moved to peel the first polish pad off, and then the first roller is moved to paste a second polish pad onto the polish spindle.

Abstract: The present invention relates to an ethylene-vinyl alcohol copolymer (EVOH) resin composition, an EVOH film formed therefrom, and a multilayer structure containing the same. The surface roughness of the EVOH resin composition is the root mean square gradient (Sdq) between 0.0005 and 13. The EVOH of the invention can reduce the torque output during processing, and make the appearance of the EVOH film highly uniform.

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material may be be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

Abstract: The present invention relates to an ethylene-vinyl alcohol copolymer (EVOH) resin composition, an EVOH film formed therefrom, and a multilayer structure containing the same. The surface roughness of the EVOH resin composition is the peak material volume (Vmp) between 0.0008 and 10 ?m3/?m2. The EVOH of the invention can reduce the torque output during processing, and can obtain the EVOH film with excellent appearance.

Abstract: A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a structure having a frontside and a backside, the structure including a substrate and a stack of a first type and a second type epitaxial layers having different material compositions alternatively stacked above the substrate, wherein the stack is at the frontside of the structure and the substrate is at the backside of the structure; patterning the stack, thereby forming a fin above the substrate; implanting a first dopant into a first region of the fin, the first dopant having a first conductivity type; implanting a second dopant into a second region of the fin, the second dopant having a second conductivity type opposite the first conductivity type; and forming a first contact on the first region and a second contact on the second region.

Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

Abstract: A testing socket includes a metal block, an assembly block, an analog ground probe pin and a digital ground probe pin. The metal block is formed with a concave portion and used to connect to an independent main ground. The assembly block is electrically isolated from the metal block, and detachably embedded in the recess, so that the metal block and the assembly block are assembled together to be a probe holder. The digital grounding probe is inserted in the metal block, electrically connected to the independent main ground through the metal block. The digital ground probe pin can be electrically connected to a device to be tested (DUT) and the independent main ground. The analog ground probe pin is inserted in the assembly block, and electrically connected to the DUT and another independent main ground.

Abstract: A device includes a semiconductor fin, a first epitaxy structure and a gate stack. The semiconductor fin protrudes from a substrate. The first epitaxy feature laterally surrounds a first portion of the semiconductor fin. The gate stack laterally surrounds a second portion of the semiconductor fin above the first portion of the semiconductor fin, wherein the second portion of the semiconductor fin has a lower surface roughness than the first epitaxy feature.

Abstract: This disclosure provides a method of protecting a subject for exercise that prevents an exercise-related harmful effect and reducing exercise fatigue in the subject to thereby enhance physical performance and promote anti-fatigue and anti-inflammatory effects in the subject.

Abstract: A planarization method includes: providing a substrate, wherein the substrate includes a first region and a second region having different degrees of hydrophobicity or hydrophilicity, the second region covering an upper surface of the first region; polishing the substrate with a polishing slurry until the upper surface of the first region is exposed; and continuing polishing and performing a surface treatment by the polishing slurry to adjust the degree of hydrophobicity or hydrophilicity of at least one of the first region and the second region. The polishing slurry and the upper surface of the second region have a first contact angle, and the polishing slurry and the upper surface of the first region have a second contact angle. The surface treatment keeps a contact angle difference between the first contact angle and the second contact angle being equal to or less than 30 degrees during the polishing.

Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.

Abstract: A dual-band transform circuit structure includes a first transmission line, a second transmission line, and a conductive layer. The first transmission line has a first input terminal, a first output terminal, and a second output terminal. The second transmission line has a second input terminal, a third input terminal, a third output terminal, and a fourth output terminal. The second input terminal is coupled to the first output terminal, and the third input terminal is coupled to the second output terminal. The conductive layer is stacked with the first transmission and the second transmission line. The conductive layer includes a first hollow pattern. The first hollow pattern and the second transmission line are overlapped in a top view.

Abstract: The purpose of the present invention is to provide an information processing device capable of executing a quantum program, including: a support vector decision unit that decides a support vector from among a plurality of pieces of teacher data; and a classification execution unit that classifies target data into a plurality of classes on the basis of the support vector, wherein the classification execution unit classifies the target data on the basis of results of time evolution computation of an energy level in the case where the target data is treated as an Ising model.

Abstract: An operation method for a memory device is provided. The operation method includes: increasing a dummy word line voltage to a first dummy word line voltage during a pre-tum on period; increasing the dummy word line voltage from the first dummy word line voltage to a second dummy word line voltage during a read period; and lowering the dummy word line voltage after the read period is finished. Wherein the first dummy word line voltage is lower than the second dummy word line voltage.

Abstract: The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.

Abstract: A low-profile offset-type spinal fusion device includes a first screw, a connection base, a nut and a compression part. The first screw has an external thread and a flange. The connection base includes a penetration part and a connection part disposed no higher than the penetration part, and can sleeve the first screw through a first hole of the penetration part to contact the flange with opposite ends of the first screw protruding out of the first hole. The nut, used to engage the first screw, has a bottom surface to contact against the penetration part. When the first screw is installed by penetrating the first hole, the nut and the flange are located to opposite ends of the first hole. The compression part is to screw into a cavity of the connection part for depressing a connecting bar tightly in the cavity.