Method for via formation in a semiconductor device
A method of via formation in a semiconductor device includes the following steps of providing a photoresist with a photoresist pattern defining an opening of a via, wherein the photoresist comprising a thermally cross-linking material is disposed on a structure layer; dry-etching the structure layer to a first depth through the opening; baking the thermally cross-linking material to reduce the opening; and dry-etching the structure layer to a second depth through the reduced opening, wherein the second depth is greater than the first depth.
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1. Technical Field
The present disclosure relates to a method for via formation, More particularly, the present disclosure relates to a method for via formation in a semiconductor device.
2. Background
The fabrication of integrated circuits on a semiconductor substrate typically includes multiple photolithography steps. A photolithography process begins with application of a thin layer of a photoresist material to the substrate surface. The photoresist is then exposed through a photolithography exposure tool to a radiation source that changes the solubility of the photoresist at areas exposed to the radiation. The photolithography exposure tool typically includes transparent regions that do not interact with the exposing radiation and a patterned material or materials that do interact with the exposing radiation, either to block it or to shift its phase.
“Masks” and “reticles” are types of lithography exposure tools, that is, tools that alter radiation to print an image on the exposed surface. The term “mask” is sometimes reserved for photolithography exposure tools that print an entire wafer in one exposure, and the term “reticle” is sometimes reserved for a photolithography exposure tool that projects a demagnified image and prints less than the entire wafer during each exposure. No matter what kinds of lithography exposure tools are used, the more lithography exposure tools the fabrication process uses, the more cost-ineffective it is, particularly if cost is a consideration.
Due to ever-increasing density in ULSI (ultra-large-scale integration) circuits, various techniques have been proposed to overcome the limits of the present semiconductor fabrication technology. For example, reduction in size of a contact via or through silicon via (TSV) has been actively pursued below the resolution limits of the current optical lithography technology.
To form a contact via or TSV, optical lithography technology has been conventionally used to form a photoresist pattern. Using the photolithography technique, patterns of a mask are transferred onto a photoresist applied on a semiconductor substrate. The photoresist is subjected to development after patterns are transferred thereto. Next, the underlying semiconductor substrate is etched using the developed photoresist pattern.
There have been various attempts to solve the resolution problem. Particularly, the extension of the optical lithography technology for sub-0.18 nm contact via lithography has been attempted. Accordingly, a need exists for a simplified and more practical method of forming a photoresist pattern for via formation under the 0.18 nm design rule. Particularly, a need exists for a method allowing precise critical dimension control using conventional optical lithography equipment such as an inexpensive i-line lithography system.
SUMMARYTo solve the problems of the above-mentioned prior art, the present disclosure discloses a method of via formation in a semiconductor device. The method comprises the following steps of providing a photoresist with a photoresist pattern defining an opening of a via, wherein the photoresist comprising thermally cross-linking material is disposed on a structure layer; dry-etching the structure layer to a first depth through the opening; baking the thermally cross-linking material to reduce the opening; and dry-etching the structure layer to a second depth through the reduced opening, wherein the second depth is greater than the first depth.
The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or to processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
Particularly, disclosed herein is a method for post lithographic critical dimension shrinking to form a via structure with greater speed and lower power consumption. It should be understood that the description of the various aspects of the present disclosure are merely illustrative and that they should not be taken in a limiting sense.
Referring to
The thick photoresist layer 30 is formed on the anti-reflection coating layer 50 as illustrated in
Referring to
In the dry-etch step 100 (e.g., anisotropic reactive ion etching (RIE)) shown in
In
A second dry-etch step 110 (e.g., anisotropic reactive ion etching (RIE)) (
In conclusion, as shown in
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims
1. A method of via formation in a semiconductor device, the method comprising the steps of;
- providing a photoresist with a photoresist pattern defining an opening of a via, wherein the photoresist is disposed on a structure layer, wherein the photoresist comprises a thermally cross-linking material;
- dry-etching the structure layer to a first depth through the opening;
- baking the thermally cross-linking material to reduce the opening; and
- dry-etching the structure layer to a second depth through the reduced opening, wherein the second depth is greater than the first depth.
2. The method of claim 1, further comprising a step of forming an anti-reflection coating layer between the photoresist and the structure layer.
3. The method of claim 2, wherein the step of dry-etching the structure layer comprises dry-etching the anti-reflection coating layer to the first depth of the structure layer.
4. The method of claim 2, wherein the second depth etching step comprises forming a trench in the structure layer under the anti-reflection coating layer.
5. The method of claim 2, wherein the second depth etching step comprises forming a hole in the structure layer under the anti-reflection coating layer.
6. The method of claim 1, wherein the structure layer is a metal layer.
7. The method of claim 1, wherein the structure layer is a polysilicon layer.
8. The method of claim 1, wherein the structure layer is a semiconductor layer.
9. The method of claim 1, wherein the structure layer is an insulation layer.
10. The method of claim 1, further comprising a step of removing the photoresist.
11. The method of claim 2, further comprising a step of removing the photoresist and the anti-reflection coating layer.
Type: Grant
Filed: May 26, 2011
Date of Patent: Mar 5, 2013
Patent Publication Number: 20120302062
Assignee: Nanya Technology Corporation (Kueishan, Tao-Yuan Hsien,)
Inventors: Chih Ching Lin (Taoyuan), Yi Nan Chen (Taipei), Hsien Wen Liu (Luzhu Township)
Primary Examiner: Charles Garber
Assistant Examiner: Reema Patel
Application Number: 13/116,432
International Classification: H01L 21/4763 (20060101);