Abstract: An electronic device includes: a body, including opposite outer and inner surfaces, and a through opening passing through the outer and inner surfaces; a fan, disposed on the outer surface and having an air outlet; a heat sink assembly, disposed at the air outlet and corresponding to the through opening; a first thermal tube, having one end assembled on the heat sink assembly and located on the side of the outer surface; a first heat source, disposed corresponding to the other end of the first thermal tube; a thermal plate, disposed in the body and corresponding to the through opening, having one side abutting against the heat sink assembly and the inner surface; a second thermal tube, having one end connected to the other side of the thermal plate; and a second heat source, disposed corresponding to the other end of the second thermal tube.

Abstract: A display apparatus and a display holding device thereof are provided. The display holding device includes a front frame and a rear plate. The front frame includes an edge portion, a top portion, a containing portion, an extending portion, and a holding portion. The top portion is connected to the edge portion. An end of the containing portion is connected to the edge portion, and the containing portion is adapted to contain an optical transceiver module. The extending portion adapted to contain a panel module is connected to an another end of the containing portion and extends toward a direction away from the edge portion. The holding portion adapted to contain a light-transmissive element is between the containing portion and the extending portion. The rear plate adapted to contain an optical film module is connected to the front frame. Therefore, a width of the front frame can be further reduced.

Abstract: In some embodiments, an integrated chip is provided. The integrated chip includes a source region and a drain region disposed in a substrate. A gate is disposed over the substrate and between the source region and the drain region. A silicide structure is disposed over the drain region. A first silicide blocking segment and a second silicide blocking segment are disposed directly over the drain region. The silicide structure continuously extends over the drain region from a first sidewall contacting the first silicide blocking segment to a second sidewall contacting the second silicide blocking segment, in a cross-sectional view.

Abstract: A computer with a function expansion mechanism includes a computer host and a function expansion device. The computer host includes a base and a functional base cover covering the base. A bottom surface of the base has a first opening, and the base is provided therein with a connector exposed from the first opening. The function expansion device includes an expansion seat, a top surface of the expansion seat has a second opening, and the expansion seat is provided therein with a docking connector exposed from the second opening. The computer host is stacked and assembled by the bottom surface at the top surface of the function expansion device, such that the first opening and the second opening are in communication with each other and the connector and the docking connector are mutually docked, thereby achieving an effect of function expansion without removal of a computer.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a first capacitor conductor disposed over an isolation structure arranged within a substrate. The isolation structure laterally extends past opposing outer sidewalls of the first capacitor conductor. A capacitor dielectric is arranged along one of the opposing outer sidewalls of the first capacitor conductor and over a top surface of the first capacitor conductor. A second capacitor conductor is arranged along an outer sidewall of the capacitor dielectric and over a top surface of the capacitor dielectric. The second capacitor conductor laterally overlaps parts of both the capacitor dielectric and the first capacitor conductor.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments between the pair of source/drain regions; and a protection structure overlapping the gate electrode.

Abstract: A fabricating method of a non-woven film, for electronic components, includes the following steps. Providing a polyetherimide substrate and an aerogel dispersion, in which the aerogel dispersion includes an aerogel, and the aerogel has a moisture content between 0.7% and 0.9% and a porosity between 85% and 95%. Dipping the polyetherimine substrate in the aerogel dispersion, such that the aerogel dispersion covers the polyetherimine substrate. Performing a thermal compression process on the polyetherimide substrate, such that the aerogel and the polyetherimide substrate are composited with each other. Performing an ultrasonic oscillating process on the polyetherimine substrate, such that the aerogel not being composited with the polyetherimine substrate is removed.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Abstract: A casing assembly includes a casing and a light emitting module. The casing is provided with an accommodation recess formed by an inner wall surface and a light outlet portion formed by two inner peripheral edges. The accommodation recess communicates with the light outlet portion. The light emitting module is disposed in the accommodation recess of the casing and located close to the light outlet portion. The light emitting module is provided with a light emitting surface, and a normal line of the light emitting surface is non-parallel and non-perpendicular to an opening direction of the light outlet portion.

Abstract: A gate oxide layer for a high voltage transistor is formed using methods that avoid thinning in the corners of the gate oxide layer. A recess is formed in a silicon substrate. The exposed surfaces of the recess are thermally oxidized to form a thermal oxide layer of the gate oxide layer. A high temperature oxide layer of the gate oxide layer is then formed within the exposed surfaces of the recess by chemical vapor deposition. The combination of the thermal oxide layer and the high temperature oxide layer results in a gate oxide layer that does not exhibit the double hump phenomenon in the drain current vs. gate voltage curve. The high temperature oxide layer may include a rim that extends out of the recess.

Abstract: An eye-diagram index analytic method includes: calculating a transfer function of multiple coupled lines; converting the transfer function into a pulse response; calculating an eye-diagram index according to the pulse response; and correcting the eye-diagram index according to peak distortion analysis.

Abstract: A driving mechanism is provided and includes a first casing, a second casing and an operating member. The second casing is arranged on the first casing. The operating member is movably mounted on one of the first casing and the second casing. When the operating member is moved from a first state to a second state, the operating member drives another one of the first casing and the second casing to move from a first predetermined position to a second predetermined position along a first vertical direction. When the operating member is moved from the second state to the first state, the another one of the first casing and the second casing moves from the second predetermined position to the first predetermined position along a second vertical direction opposite to the first vertical direction.

Abstract: Some embodiments relate to an integrated circuit device incorporating an etched recessed gate dielectric region. The integrated circuit device includes a substrate including a first upper surface, a gate dielectric region disposed at the first upper surface of the substrate and extending into the substrate, and a gate structure disposed over the gate dielectric region. The gate dielectric region includes a second upper surface and forms a recess extending below the second upper surface. The second upper surface includes a perimeter portion surrounding the recess. The gate structure completely covers the second upper surface of the gate dielectric region and extends into the recess.

Abstract: A semiconductor structure includes a substrate, an isolation structure disposed in the substrate, and a hybrid structure disposed over the isolation structure. The hybrid structure is substantially conformal with respect to a profile of the isolation structure. The hybrid structure includes an oxide component, a nitride component surrounding the oxide component, and a first polysilicon component alongside the nitride component. The nitride component includes a first upper surface closed to the first polysilicon component, and a second upper surface distal to the first polysilicon component. The second upper surface is lower than the first upper surface.

Abstract: A casing with a replacement structure includes the casing and a replacement assembly. The casing includes a casing body and an assembly space. The assembly space is provided in a recessed manner at the casing body and is located at a vertical intersection of two side edges of the casing body. The replacement assembly includes a frame, which is installed in the assembly space and encloses with the casing body to form an accommodating space.

Abstract: A non-woven film for electronic components is provided in the present disclosure. The non-woven film for electronic components includes a polyetherimide substrate and an aerogel. The aerogel is disposed on the polyetherimide substrate. The aerogel has a moisture content between 0.7% and 0.9% and a porosity between 85% and 95%.