Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate, a gate electrode, a gate dielectric layer, first protection structures, a second protection structure and an insulating layer. The gate electrode is disposed within the substrate. The gate dielectric layer is disposed within the substrate and laterally surrounds the gate electrode. The first protection structures are disposed over the gate electrode. The second protection structure is disposed over the gate dielectric layer. The insulating layer is between the second protection structure and the gate dielectric layer.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures formed in an array disposed over the gate electrode; and a second protection structure comprising a ring shape from a top-view perspective, and disposed over the gate dielectric layer and at a same level as the plurality of first protection structures from a cross-sectional view.

Abstract: The present disclosure discloses a memory access interface device. A signal training circuit is configured for performing following steps. A transmitting circuit transmits a training data signal and a training data strobe signal as an output data signal and an output data strobe signal to a memory device according to timing reference signals. A read data signal from the memory device is received. The training data signal and the read data signal are compared to generate a comparison result indicating whether the read data signal matches the training data signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of one of the timing reference signals, further modifying the timing of one of the training data signal and the training data strobe signal, to be one of under-test phases to execute a new loop of a training process.

Abstract: A delivery chain apparatus of wood-working machine with saw blades is disclosed. The delivery chain apparatus is formed into a loop by pivoting track units. The surface of each track unit is provided at least with a chain, each chain is locked on the track unit, some chains are made of metal, and the surface of a metallic chain is provided with teeth. The delivery device revolves on a desktop by power to send wood boards below the saw blades. The present invention is characterized in that the chains on the track units of the delivery device are combination of non-skid chains and the metallic chains, with the non-skid chains being made of rubber.

Abstract: An electronic device includes a casing and a waterproof lid structure. The casing has an opening. The waterproof lid structure corresponds in position to the opening and includes a supportive sheet metal, waterproof component, movable latch lid and bolts. The supportive sheet metal has an axle pivotally connected to one side of the opening. The waterproof component hermetically seals the opening and lies on one side of the supportive sheet metal. The movable latch lid covers the other side of the supportive sheet metal and is penetrated by passages. The bolts correspond in position to the passages, respectively, and each include a rod portion and a head portion disposed at one end of the rod portion. The rod portions pass through the passages and supportive sheet metal to get fastened to the waterproof component, allowing the head portions to stop at the outer side of the movable latch lid.

Abstract: A slide rail mechanism includes a first slide rail assembly, a second slide rail assembly, a third slide rail assembly and a locking member. An opening movement of a second rail of the first slide rail assembly with respect to a first rail of the first slide rail assembly drives the locking member from a first predetermined position to a second predetermined position, and an opening movement of a second rail of the second slide rail assembly with respect to a first rail of the second slide rail assembly drives the locking member from the second predetermined position to a third predetermined position. The locking member at the third predetermined position blocks the third working member for preventing an opening movement of a second rail of the third slide rail assembly with respect to a first rail of the third slide rail assembly.

Abstract: A backlight module is provided and includes a circuit board, a light emitting component disposed on the circuit board, a light guiding component, a first light reflecting component and a second light reflecting component. The first light reflecting component covers at least a portion of a first surface of the light guiding component adjacent to the circuit board. The second light reflecting component includes a first light reflecting portion and a second light reflecting portion. The first light reflecting portion extends along a first direction and covers at least a portion of a second surface of the light guiding component away from the circuit board. The second light reflecting portion is connected to the first light reflecting portion and extends along a second direction. The second reflecting portion is located corresponding to a third surface of the light guiding component. Besides, a related light emitting electronic device is provided.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.

Abstract: A homogeneous composite substrate includes a woven cloth and at least one fiber membrane. The woven cloth includes a plurality of first fibers. The fiber membrane is disposed on at least one surface of the woven cloth, and the fiber membrane includes a plurality of second fibers, in which a material of the first fibers and a material of the second fibers are the same, a fiber diameter of each first fiber is larger than or equal to 20 ?m and smaller than or equal to 130 ?m, and a fiber diameter of each second fiber is larger than or equal to 3 ?m and smaller than or equal to 10 ?m.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate dielectric layer and contacting the gate dielectric layer; and a pair of source/drain regions on opposing sides of the gate dielectric layer.

Abstract: A backlight module is provided and includes a circuit board, a light emitting component disposed on the circuit board, a light guiding component, a first light reflecting component and a second light reflecting component. The first light reflecting component covers at least a portion of a first surface of the light guiding component adjacent to the circuit board. The second light reflecting component includes a first light reflecting portion and a second light reflecting portion. The first light reflecting portion extends along a first direction and covers at least a portion of a second surface of the light guiding component away from the circuit board. The second light reflecting portion is connected to the first light reflecting portion and extends along a second direction. The second reflecting portion is located corresponding to a third surface of the light guiding component. Besides, a related light emitting electronic device is provided.

Abstract: A photosensitive device is provided. The photosensitive device includes a sensing stack, an anti-reflective layer, an optical filter, a first electrode, and a second electrode. The sensing stack includes a first semiconductor layer, an intrinsic semiconductor layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the intrinsic semiconductor layer. The anti-reflective layer is disposed on a side of the sensing stack. The optical filter is disposed on the anti-reflective layer and blocks input light with an incident angle greater than 50 degrees. The first electrode and the second electrode are disposed on the sensing stack.

Abstract: The present invention discloses a data transmission apparatus having clock gating mechanism. Each of data transmission circuits has a flip-flop depth of N and receives a write clock signal and one of read clock signals to receive and output one of data signals. A write clock gating circuit receives a write clock gating enabling signal to transmit the write clock signal to the data transmission circuits. Each of read clock gating circuits receives one of read clock gating enabling signals to transmit one of the read clock signals. The gating signal transmission circuit has a flip-flop depth of N+M and receives the write and the read clock signals to receive the write clock gating enabling signal and output the read clock gating enabling signals. A largest timing difference among the read clock signals is P clock cycles and M is at least ?P?.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

Abstract: Transistors with improved saturation drain current and methods for making such transistors are disclosed. The gate is formed in the shape of a longitudinal trench and a plurality of lateral trenches below the longitudinal trench. The resulting dual-recess structure increases the surface area of the gate, which permits additional charge carriers and increases the saturation drain current of the transistor. Such transistors can be useful in high voltage and medium voltage applications such as in display driver integrated circuits.

Abstract: A failure diagnostic system of a motor encoder is disclosed and includes a motor, an encoder, a servo driver, and a safety module. The servo driver controls the motor through a current command. The safety module continuously obtains a feedback position of the motor through the encoder. When the safety module determines based on the feedback position that the current state of the motor is consistent with a pre-determined disturbance condition, the safety module requests the servo driver to output an additional current command to disturb the motor. Next, the safety module determines whether the encoder is failure based on a variation of following feedback position.

Abstract: Disclosed is a DDR SDRAM signal calibration device capable of adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and a DQS signal; and a calibration circuit configured to generate a first delay signal according to the DQS enablement setting signal and generate a second delay signal according to the first delay signal, the calibration circuit further configured to generate a calibration signal according to the first and second delay signals and the DQS signal. The enablement signal setting circuit maintains or adjusts the DQS enablement setting according to the calibration signal.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.

Abstract: A homogeneous composite substrate includes a woven cloth and at least one fiber membrane. The woven cloth includes a plurality of first fibers. The fiber membrane is disposed on at least one surface of the woven cloth, and the fiber membrane includes a plurality of second fibers, in which a material of the first fibers and a material of the second fibers are the same, a fiber diameter of each first fiber is larger than or equal to 20 ?m and smaller than or equal to 130 ?m, and a fiber diameter of each second fiber is larger than or equal to 3 ?m and smaller than or equal to 10 ?m.