Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

Abstract: A slide rail mechanism includes a first slide rail assembly, a second slide rail assembly, a third slide rail assembly and a locking member. An opening movement of a second rail of the first slide rail assembly with respect to a first rail of the first slide rail assembly drives the locking member from a first predetermined position to a second predetermined position, and an opening movement of a second rail of the second slide rail assembly with respect to a first rail of the second slide rail assembly drives the locking member from the second predetermined position to a third predetermined position. The locking member at the third predetermined position blocks the third working member for preventing an opening movement of a second rail of the third slide rail assembly with respect to a first rail of the third slide rail assembly.

Abstract: A display apparatus and a display holding device thereof are provided. The display holding device includes a front frame and a rear plate. The front frame includes an edge portion, a top portion, a containing portion, an extending portion, and a holding portion. The top portion is connected to the edge portion. An end of the containing portion is connected to the edge portion, and the containing portion is adapted to contain an optical transceiver module. The extending portion adapted to contain a panel module is connected to an another end of the containing portion and extends toward a direction away from the edge portion. The holding portion adapted to contain a light-transmissive element is between the containing portion and the extending portion. The rear plate adapted to contain an optical film module is connected to the front frame. Therefore, a width of the front frame can be further reduced.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

Abstract: A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.

Abstract: A semiconductor structure and forming method thereof are provided. A substrate includes a first region, a second region, and a boundary region defined between the first region and the second region. An isolation structure is disposed in the boundary region. An upper surface of the isolation structure has a stepped profile. A first boundary dielectric layer and a second boundary dielectric layer are disposed over the isolation structure. The first boundary dielectric layer is substantially conformal with respect to the stepped profile of the isolation structure.

Abstract: An electronic device includes a casing, a cover, and a waterproof element. The casing has an opening. The cover is covered and assembled at the opening. The waterproof element includes a double-sided tape and an elastic body. The double-sided tape includes a first substrate, a first adhesive layer, and a second adhesive layer. The first adhesive layer and the second adhesive layer are coated on two opposite surfaces of the first substrate, respectively. The elastic body is fixed on the casing or the cover, adhered to the second adhesive layer, and tightly fitted to the cover or the casing repeatedly through the first adhesive layer.

Abstract: Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material.

Abstract: A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The a semiconductor structure includes: a substrate; a gate electrode disposed within the substrate; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate electrode adjacent to the plurality of first structures; and an insulating layer between the second protection structure and the gate electrode.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate, a gate electrode, a gate dielectric layer, first protection structures, a second protection structure and an insulating layer. The gate electrode is disposed within the substrate. The gate dielectric layer is disposed within the substrate and laterally surrounds the gate electrode. The first protection structures are disposed over the gate electrode. The second protection structure is disposed over the gate dielectric layer. The insulating layer is between the second protection structure and the gate dielectric layer.

Abstract: The present disclosure discloses a memory access interface device. A signal training circuit is configured for performing following steps. A transmitting circuit transmits a training data signal and a training data strobe signal as an output data signal and an output data strobe signal to a memory device according to timing reference signals. A read data signal from the memory device is received. The training data signal and the read data signal are compared to generate a comparison result indicating whether the read data signal matches the training data signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of one of the timing reference signals, further modifying the timing of one of the training data signal and the training data strobe signal, to be one of under-test phases to execute a new loop of a training process.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures formed in an array disposed over the gate electrode; and a second protection structure comprising a ring shape from a top-view perspective, and disposed over the gate dielectric layer and at a same level as the plurality of first protection structures from a cross-sectional view.

Abstract: A delivery chain apparatus of wood-working machine with saw blades is disclosed. The delivery chain apparatus is formed into a loop by pivoting track units. The surface of each track unit is provided at least with a chain, each chain is locked on the track unit, some chains are made of metal, and the surface of a metallic chain is provided with teeth. The delivery device revolves on a desktop by power to send wood boards below the saw blades. The present invention is characterized in that the chains on the track units of the delivery device are combination of non-skid chains and the metallic chains, with the non-skid chains being made of rubber.

Abstract: An electronic device includes a casing and a waterproof lid structure. The casing has an opening. The waterproof lid structure corresponds in position to the opening and includes a supportive sheet metal, waterproof component, movable latch lid and bolts. The supportive sheet metal has an axle pivotally connected to one side of the opening. The waterproof component hermetically seals the opening and lies on one side of the supportive sheet metal. The movable latch lid covers the other side of the supportive sheet metal and is penetrated by passages. The bolts correspond in position to the passages, respectively, and each include a rod portion and a head portion disposed at one end of the rod portion. The rod portions pass through the passages and supportive sheet metal to get fastened to the waterproof component, allowing the head portions to stop at the outer side of the movable latch lid.

Abstract: A slide rail mechanism includes a first slide rail assembly, a second slide rail assembly, a third slide rail assembly and a locking member. An opening movement of a second rail of the first slide rail assembly with respect to a first rail of the first slide rail assembly drives the locking member from a first predetermined position to a second predetermined position, and an opening movement of a second rail of the second slide rail assembly with respect to a first rail of the second slide rail assembly drives the locking member from the second predetermined position to a third predetermined position. The locking member at the third predetermined position blocks the third working member for preventing an opening movement of a second rail of the third slide rail assembly with respect to a first rail of the third slide rail assembly.

Abstract: A backlight module is provided and includes a circuit board, a light emitting component disposed on the circuit board, a light guiding component, a first light reflecting component and a second light reflecting component. The first light reflecting component covers at least a portion of a first surface of the light guiding component adjacent to the circuit board. The second light reflecting component includes a first light reflecting portion and a second light reflecting portion. The first light reflecting portion extends along a first direction and covers at least a portion of a second surface of the light guiding component away from the circuit board. The second light reflecting portion is connected to the first light reflecting portion and extends along a second direction. The second reflecting portion is located corresponding to a third surface of the light guiding component. Besides, a related light emitting electronic device is provided.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.