Abstract: Disclosed is a DDR SDRAM signal calibration device capable of adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and a DQS signal; and a calibration circuit configured to generate a first delay signal according to the DQS enablement setting signal and generate a second delay signal according to the first delay signal, the calibration circuit further configured to generate a calibration signal according to the first and second delay signals and the DQS signal. The enablement signal setting circuit maintains or adjusts the DQS enablement setting according to the calibration signal.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.

Abstract: A homogeneous composite substrate includes a woven cloth and at least one fiber membrane. The woven cloth includes a plurality of first fibers. The fiber membrane is disposed on at least one surface of the woven cloth, and the fiber membrane includes a plurality of second fibers, in which a material of the first fibers and a material of the second fibers are the same, a fiber diameter of each first fiber is larger than or equal to 20 ?m and smaller than or equal to 130 ?m, and a fiber diameter of each second fiber is larger than or equal to 3 ?m and smaller than or equal to 10 ?m.

Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

Abstract: During operation, a computer system may provide instructions to access points in an indoor environment to measure relative distances between the access points. Then, the computer system may receive the measured relative distances. Moreover, the computer system may calculate geographic locations of the access points based at least in part on the measured relative distances. Next, the computer system may select potential anchor access points in the access points, and may provide, to an electronic device, information specifying the potential anchor access points. Furthermore, the computer system may receive, from the electronic device, second information specifying anchor access points in the potential access points and defined locations of the anchor access points. Additionally, the computer system may update the geographic locations based at least in part on the defined of the anchor access points, and may provide, to the access points, the updated geographic locations.

Abstract: A replacement device includes a replacement module and a slider. The replacement module includes a sliding portion. The sliding portion is provided with a limiting column, which is formed with a fixing hole. The slider includes a slider body. The slider body is provided with a first latch, a limiting hole and a fixing element, wherein the first latch is arranged on a first side edge of the slider body. The slider is correspondingly arranged on the sliding portion of the replacement module, and the limiting column of the sliding portion passes through the limiting hole. The fixing element has a top portion, and is fixed in the fixing hole. The size of the top portion is greater than the size of the limiting hole, so that the slider moves relative to the replacement module within a limit range of the limiting hole.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Abstract: A monitor includes a casing assembly, a light-emitting module and a display panel. The casing assembly includes a casing and a support frame. The support frame is disposed in the casing. The support frame includes an accommodation portion and at least one support portion, the accommodation portion is connected to the casing, the support portion is connected to the accommodation portion and protrudes from the accommodation portion. The light-emitting module is disposed in the accommodation portion. The display panel is supported by the at least one support portion.

Abstract: A bracket device of a slide rail assembly includes a longitudinal wall and a mounting member. The mounting member is movable relative to the longitudinal wall along a height direction of the longitudinal wall. When the bracket device is rotated to be switched from a first state to a second state, the mounting member is configured to be moved from a first position to a second position. When the mounting member is located at the first position, the mounting member is operable to be mounted to a rack. When the mounting member is located at the second position, the mounting member is prevented from being mounted to the rack.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a source region, a drain region, a gate region and a gate oxide. The gate region is disposed between the source region and the drain region. The gate oxide is disposed on the gate region. A bottom interface is between the gate region and the gate oxide, and an entire of the bottom interface is substantially flat.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises an insulating structure, a dielectric structure, a metal structure, a conductive spacer and a dielectric spacer. The dielectric structure is formed on the insulating structure. The metal structure is formed on and surrounded by the dielectric structure. A bottom surface and a lateral surface of the metal structure are in direct contact with the dielectric structure. The conductive spacer is formed on the insulating structure. The conductive spacer surrounds the dielectric structure. The dielectric spacer is formed on the insulating structure, wherein the dielectric spacer surrounds the conductive spacer.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments between the pair of source/drain regions; and a protection structure overlapping the gate electrode.

Abstract: The present invention discloses a data transmission apparatus having clock gating mechanism. Each of data transmission circuits has a flip-flop depth of N and receives a write clock signal and one of read clock signals to receive and output one of data signals. A write clock gating circuit receives a write clock gating enabling signal to transmit the write clock signal to the data transmission circuits. Each of read clock gating circuits receives one of read clock gating enabling signals to transmit one of the read clock signals. The gating signal transmission circuit has a flip-flop depth of N+M and receives the write and the read clock signals to receive the write clock gating enabling signal and output the read clock gating enabling signals. A largest timing difference among the read clock signals is P clock cycles and M is at least [P].

Abstract: A retractable assembly includes a fixed frame, a movable frame and a plurality of first balls. The fixed frame has an accommodation portion and a plurality of guiding portions. The guiding portions are connected to the accommodation portion. The movable frame is at least partially located in the accommodation portion. The first balls are movably located in the guiding portions, and the movable frame is connected to the fixed frame via the first balls.

Abstract: A light-emitting device is applicable to a backlight module. The light-emitting device includes a substrate, a light-emitting diode (LED) and an encapsulation body. The encapsulation body is on the substrate and covers the LED. The encapsulation body includes a base and a lens. The base has a base surface. The lens has a lens surface. The lens surface conforms to a cubic Bezier curve. The cubic Bezier curve has a start point and an end point. The start point of the cubic Bezier curve is at the base surface. The end point of the cubic Bezier curve corresponds to the center of the LED. The lens surface is provided with a concave portion at the end point. The lens increases the light-emitting angle of the LED, so that the spacing between light-emitting devices can be increased, thereby reducing the number of light-emitting devices to be used and the costs.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Abstract: Interlayer dielectric (ILD) layer(s) of a semiconductor device may be configured as a gate oxide for high-voltage transistors, and therefore additional process operations to deposit dedicated gate oxide layers are not needed. Moreover, additional processing operations to form the gate structures of the high-voltage fin-based PMOS transistors and high-voltage fin-based NMOS transistors are not needed in that middle end of line (MEOL process and back end of line (BEOL) processes can be used as the gate formation process of the high-voltage transistors.

Abstract: A semiconductor structure includes a substrate, a first FET device and a second FET device. The substrate has a first region and a second region. The first FET device is in the first region, and the second FET device is in the second region. The first FET device includes a first isolation structure, a first gate electrode disposed over a portion of the first isolation structure, and a first gate dielectric layer between the substrate and the first gate electrode. The first gate dielectric layer has a first thickness. The second FET device includes a plurality of fin structures, a plurality of second isolation structures, a second gate electrode over the plurality of fin structures, and a second gate dielectric layer between the second gate electrode and the plurality of fin structures. The second gate dielectric layer has a second thickness. The second thickness is less than the first thickness.