Chih-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a pad barrier layer caps a pad of a piezoelectric device. The pad barrier layer is configured to block hydrogen ions and/or other errant materials from diffusing to the piezoelectric layer. Absent the pad barrier layer, hydrogen ions from hydrogen-ion containing processes performed after forming the pad may diffuse to the piezoelectric layer along a via extending from the pad to the piezoelectric device. By blocking diffusion of hydrogen ions and/or other errant materials to the piezoelectric device, the pad barrier layer may prevent delamination and breakdown of the piezoelectric layer. Hence, the pad barrier layer may prevent failure of the piezoelectric device.
Abstract: There is provided a thermometer structure including a circuit board, an infrared thermometer, a heat sink and a metal block. The infrared thermometer is arranged on the circuit board and electrically connected thereto. The heat sink is arranged on the circuit board and covers the infrared thermometer. The metal block is in contact with at least one of the circuit board and the heat sink to stabilize a local temperature of the thermometer structure.
April 29, 2022
February 2, 2023
Yen-Chang CHU, Po-Wei YU, Yen-Po CHEN, Chih-Ming SUN
Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
Abstract: A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.
Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The fin field effect transistor (FinFET) device structure includes a second fin structure adjacent to the first fin structure, and a material layer formed over the fin structure. The material layer and the isolation structure are made of different materials, the material layer has a top surface with a top width and a bottom surface with a bottom width, and the bottom width is greater than the top width.
Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.
Abstract: A fluid immersion cooling system includes a fluid tank that contains a layer of a dual-phase coolant fluid and one or more layers of single-phase coolant fluids. The dual-phase and single-phase coolant fluids are immiscible, with the dual-phase coolant fluid having a lower boiling point and higher density than a single-phase coolant fluid. A substrate of an electronic system is submerged in the tank such that high heat-generating components are immersed at least in the layer of the dual-phase coolant fluid. Heat from the components is dissipated to the dual-phase coolant fluid to generate vapor bubbles of the dual-phase coolant fluid. The vapor bubbles rise to a layer of a single-phase coolant fluid that is above the layer of the dual-phase coolant fluid. The vapor bubbles condense to droplets of the dual-phase coolant fluid. The droplets fall down into the layer of the dual-phase coolant fluid.
Abstract: A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.
Abstract: The invention comprises a light emitting diode chip and a package substrate. The light emitting diode chip is provided with a semiconductor epitaxial structure, a lateral extending interface structure, a chip conductive structure, an N-type electrode located above the semiconductor epitaxial structure and a P-type bypass detection electrode located on the lateral extending interface structure. The chip conductive structure is provided with a P-type main electrode located on a lower side. The package substrate comprises a plurality of electrode contacts through which the N-type electrode, the P-type bypass detection electrode and the P-type main electrode are connected, and a process quality of a alternative substrate adhesive layer in one of the semiconductor epitaxial structure and the chip conductive structure and a chip-substrate bonding adhesive layer between the P-type main electrode and the package substrate is evaluated by detecting electrical characteristics.
Abstract: A package substrate comprises first, second and third electrical test contacts, wherein the package substrate is provided with an upper element plane and a lower SMD electrode plane on two sides. The side edge of the upper element plane is provided with first and second electrodes of the main element and first and second electrodes of the secondary element. The main element of LED chip is electrically connected between the first and second electrodes of the main element, a parallel circuit secondary element is electrically connected between the first and second electrodes of the secondary element. The electrical characteristics of the main element of LED chip and the parallel circuit secondary element are measured through the first, second, and third electrical test contacts when electrically connected.
Abstract: A system for processing a semiconductor wafer is provided. The system includes a processing tool. The system also includes gas handling housing having a gas inlet and a gas outlet. The system further includes an exhaust conduit fluidly communicating with the processing tool and the gas inlet of the gas handling housing. In addition, the system includes at least one first filtering assembly and at least one second filtering assembly. The first filtering assembly and the second filtering assembly are positioned in the gas handling housing and arranged in a series along a flowing path that extends from the gas inlet to the gas outlet of the gas handling housing. Each of the first filtering assembly and the second filtering assembly comprises a plurality of wire meshes stacked on top of another.
July 16, 2021
January 19, 2023
CHIH-MING TSAO, PO-CHENG CHEN, DENG-AN WANG
Abstract: A compound of Formula (I) below, or a pharmaceutically acceptable salt, stereoisomer, solvate, or prodrug thereof: (I), in which Ra, Rb, Rc, Rd, X1, X2, R1-R4, W, Z, and L are defined as in the SUMMARY section. Further disclosed are a method of using the above-described compound, salt, stereoisomer, solvate, or prodrug for treating HBV infection and a pharmaceutical composition containing same.
Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.
Abstract: An electronic device including a substrate, a plurality of first signal lines, and a plurality of second signal lines is provided. The first signal lines are disposed on the substrate. Each of the first signal lines includes a first intersecting section and a first extending section. The first intersecting section each has a constant extending direction. The first intersecting section is connected to the first extending section, while the first intersecting section and the first extending section have different extending directions. The second signal lines are disposed on the substrate. Each of the second signal lines includes a second intersecting section. The second intersecting section each has a constant extending direction. The second signal lines intersect with the first signal lines to form a plurality of intersections on each of the first signal lines, and the intersections are located on the first intersecting sections.
Abstract: A DNN hardware accelerator and an operation method of the DNN hardware accelerator are provided. The DNN hardware accelerator includes: a network distributor for receiving an input data and distributing respective bandwidth of a plurality of data types of a target data amount based on a plurality of bandwidth ratios of the target data amount; and a processing element array coupled to the network distributor, for communicating data of the data types of the target data amount between the network distributor based on the distributed bandwidth of the data types.
January 15, 2019
Date of Patent:
January 10, 2023
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Abstract: A modular vehicle body includes a pair of outer frames. An inner board space with a fixed width is defined between the outer frames. Each outer frame includes a front side board and a door sill. The front side board includes a main board provided with a vertical board having a predetermined width. A first flange is provided on a side of the vertical board. The door sill includes an inner board provided with a horizontal board having a predetermined width. A second flange is provided on a side of the horizontal board. The inner board is fixedly coupled to the main board. The first flange and the second flange form an outer edge. A width between the outer edges of the pair of outer frames is set to correspond to a width of a vehicle body.
March 31, 2021
Date of Patent:
January 10, 2023
Foxtron Vehicle Technologies Co., Ltd.
Chia-Hong Chen, Kai-Wei Tseng, Chih-Ming Lai
Abstract: A method of forming a semiconductor structure is provided. The method includes forming a gate structure over an active region of a substrate, forming an epitaxial layer comprising first dopants of a first conductivity type over portions of the active region on opposite sides of the gate structure, applying a cleaning solution comprising ozone and deionized water to the epitaxial layer, thereby forming an oxide layer on the epitaxial layer, forming a patterned photoresist layer over the oxide layer and the gate structure to expose a portion of the oxide layer, forming a contact region including second dopants of a second conductivity type opposite the first conductivity type in the portion of the epitaxial layer not covered by the patterned photoresist layer, and forming a contact overlying the contact region.
Abstract: Video processing methods and apparatuses for processing a current block in a current picture by reference picture resampling include receiving input data of the current block, determining a scaling window of the current picture and a scaling window of a reference picture. The current picture and reference picture may have different scaling window sizes. A ratio between a scaling window width, height, or size of the current picture and a scaling window width, height, or size of the reference picture is constrained to be within a ratio constraint. A reference block is generated from the reference picture according to the ratio, and used to encode or decode the current block.
Abstract: A wavelength conversion element includes a substrate, a wavelength conversion layer and a fixed ring. The fixed ring has a first surface, a second surface, and a plurality of flow guiding structures. The second surface has a first region and a second region. The plurality of flow guiding structures is located on the first surface, and each of the plurality of flow guiding structures is formed with a first flow guiding hole. The first flow guiding hole extends from the first surface to the second region of the second surface. The plurality of flow guiding structures respectively have a spoiler surface, the spoiler surface stands on the first surface and has a second flow guiding hole, in which the second flow guiding hole and the first flow guiding hole of each of the plurality of flow guiding structures face different directions. A projection device of the invention is further provided.
Abstract: Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.